How to design a DDS filter design for 200 MHz?

I will be designing a clock generator that will operate from 0 up to 200MHz, the dds from Analog has a Low pass Filter of 120Mhz cut off. This filter was to eliminate the jitter on the output before beeing fed to internal comparator.

If i will design a 200MHz DDS, is this filter be the same? if not can any body tell me how to design a filter for 200MHz max output frequency output for this?

The filter has nothing to do with jitter. It is there to eliminate the output frequency alias. If you run a DDS at a clock of 300 MHz, for example, and program it to have a 10 MHz output, the DDS will also have a 290 MHz output. The lowpass filter is designed to eliminate that alias, at 290 MHz in this example. If you have a fast enough DAC in the DDS, the alias will be at the same amplitude as the desired output, and needs to be filtered.

thanks biff44,

i think i need to read more regarding this DDS design.

can you recomend any website other than that from the ANALOG technical tutorial?

blastronics

If the output frequency is considerably lower than clock/2, then the alias amplitude is quite small. It looks like tiny stair steps on an oscilloscope. As the desired output frequency approaches clock/2, then the alias grows to have similar amplitude, and it becomes more difficult to filter out.

im now considering the design of DDS of 1GSPS ( AD9858) this will be more than enough to provide an output of 200MHz,.

again, the filter given by the analog was a low pass filter of 120MHz. if i understand it functionality, this filter will also block the signal that i wanted. that is the 200MHz. not to mention other allias signals produce.

Does this means that i will redesign the filter to have a bandpass filter greater than 200MHz?

β

Yes, build a 200 MHz low-pass filter. Or slightly higher if you need flat amplitude all the way to 200 MHz.

Check out this primer on DDS operation:

www.ieee.li/pdf/viewgraphs_dds.pdf

Underclocking operation starts around page 17. 99% of the applications constrain the RF output to be less than the clock frequency. But there is no particular reason that you could not operate above the clock frequency. The amplitude (theoretically) will be degraded by the SINC function shown, and practically limited by the DAC speed.

For underclocked applications, you need to use a bandpass filter, as the clock energy and the fundamental output (remember you will be using an aliased output frequency) will dominate the output power if you use a Lowpass.

A good way to come up to speed quickly is to get one of those demonstration boards from analog devices, hook it up to a laptop and spectrum analyzer, jumper over the on-board lowpass filter, and screw around until it all makes sense. It helps if you know a little about sampling theory too.

biff44, that would be an excellent suggestion if he hadn't said "0 up to 200MHz". ;)

Oh! Not enough coffee. Yeah, you need a lowpass filter, probably with a cuttoff of 210 MHz or so, if you want to output 0 to 200 MHz signal. I thought he was looking for a single frequency output.

Probably need a clock of 500 MHz, or so.

GUYS!

dds from analog has has a sampling rate of 400GSPS then the next chip has a sample of 1GSPS. i gues i will use this chip and operate it at atleast 500MSPS? or Better yet at 1GSPS?

thanks.

I have ask for samples of lowpass filter module from coil craft, this has a pass band of 300Mhz. This would save me from layout considerations.

this Filter has 7nodes filter.