how to define the Reference frequency and channel space?

I want to design PLL circuit,and i confuse the selection of the reference frequency and channel space.I check some document,it is selected by 12.5kHz,25KHz and 50KHz and the channel space is selected the same frequency.Why not to select other frequency(<30MHz)?
And any other rule to define the reference frequency and channel space?
anybody can help me?
Thanks in advance.

By channel space do you mean in a radio receiver where this PLL is providing the local oscillator frequency?

Many PLL chips can only divide by integer numbers. So lets say you need a 50 KHz channel spacing in the PLL microwave output frequency, such as 1000 MHz, 1000.05 MHz, 1000.1 MHz..., one way to do this is to have a reference frequency of 50 KHz, and have a divisor N operating on the microwave output, where N is 20000, 20001, 20002.

You could just as easily have a reference of 25 KHz, and use an N divisor of 40000, 40002, 40004. If you did this, the microwave phase noise would be 6 dB worse over the original example above for frequency offsets inside of the control loop bandwidth. Sometimes that additional phase noise is a problem.

Some of the newer PLL chips use fractional N dividers, so you can use a higher reference frequency and still get the channel spacing that you need. Lets say you once again wanted 1000, 1000.05, and 1000.1 MHz channels. You could choses a reference frequency of 800 KHz, and use the following divisor N= 1250, 1250 1/16, 1250 2/16.

Does that help?

Thanks,biff44.You mean that the channel space selection is determined the type of communication(narrowband or wideband),and higher comparision frequency always can get better phase noise?What cause the problem cause we always select the loop bandwidth is Wn/10?

Added after 10 minutes:

The loop band width is Wr/10.

Well, synthesizer phase noise is a complicated topic. The VCO phase noise itself can not be higher than the open loop gain available to reduce it in the PLL control loop. The PLL chip itself has divider and phase detector noise floors that are often the determining factor, so one tends to want the reference frequency to be as high as possible to mitigate this chip noise. The reference oscillator itself has noise that, especiall close to the carrier, can dominate the output noise. The op amps used in the loop filter sometimes contribute to phase noise. The voltage regulators feeding the PLL circuit and especially the VCO contribute to phae noise.

Chosing the loop bandwidth for optimum phase noise is a delicate balancing act between all of these noise sources.

Thanks,Biff44.Your reply is great helful to me.And how to reduce the PLL phase noise to get a perfect sound quality?Only a way to design a perfect loop filter to do it?