Timestep errors when designing PLL in ADS

hi
i am currentlu doing a pll design in ads. I have done the same design in Microwave office and it worked. but the design in ads is giving some timestep errors. pls help.

if you r using the transient analysis in ads......change the time step to a lower value. it will work. i had the same problem.

thanks....it improves the situation a little. thanks a lot