Check if you understand Shaeffer's LNA Q=4 theory
So, here I have some Questions for all the LNA designer who take Q=4 as a rule of thumb.
The following picture shows a common source stage with source degeneration,the output noise current is measured as Iout, the source impedance is Rs. And, Lg and Ls are design to resonate with Cgs at specified operation frequency, and they are ideal inductor, BUT, ωt*Ls IS NOT EQUAL TO Rs. Under these conditions, the noise factor F equals F1,
Q1: If I Lg ≠ Ls and I interchange the value Lg and Ls, the resonant frequency should be unchanged, but if the new noise factor is F2, what's the relationship between F1 and F2?
(1) F1 > F2
(2) F1 = F2
(3) F1 < F2
(4) I don't know exactly, but I'm sure F1 ≠F2
Q2: While I derived the W and L of the transistor with Q = 4, it has a good noise factor. But if I want a better noise performance, should I
(1) Impossible! You can not find a better noise factor.
(2) Increase power dissipation, while keeping Q=4 and ωt unchanged
(3) Decrease power dissipation, while keeping Q=4 and ωt unchanged
(4) Change Q, whle keeping ωt unchanged
Q3: If I did not read the book, I may chose Q=2 or Q=8, namely, half or double the Q value, this might cause 1dB deviation to NF(dB) under the same power dissipation, thousand thanks for saving me from such a terrible mistake.
(1) Yes
(2) No
Q4: The Q = 4 is derived under input power matched condition
(1) Yes!
(2) No!
(3) It was derived from power matched condition, but it could be extanded to mis-match condition.
you could see this paper, it explain four methods for lna optimization. i think it helpful to understand, even though i can't agree with the fourth methods completely. maybe i can't grasp it! i hope it will help you
"CMOS Low-Noise Amplifier Design Optimization Techniques"
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. VOL.52,NO.5,MAY 2004
? I think there is a misunderstand. I post the question to ask people who recommand Shaeffer's book and papers for LNA design. I want to discuss the theory with somebody interested in his theory. But I have to thank you for your recommandation of a great paper, I'll take some time to read it.
according to the "Bible(:))"my answer to Q1 is (4). yeah, the resonant frequency is unchanged, however, the input circuit Q is changed (meanwhile, the 50ohm input matching crashed), so the NF is changed (if Lg>Ls, i think the answer is F2>F1 due to the decrease of the Q and vice versa).
according to the Fig.10 of that paper, the answer to the Q2 is clearly (2) i think
may i derive ur 3rd question as this: quality factor Q of the input matching network (either internal or external matching network provided) does not affect the NF so much? if the answer is yes, can we do the matching in whatever way we could, without considering the Q of the matching network?
BTW, a new paper namely the "Corrections to “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier”, IEEE, JSSC, VOL.40, NO.6, JUNE 2005 said the Q is revised to Q(L,opt,Pd)>=2.598, so, Q=4 is a saga now.
am i wrong?
Dear Neo, thank you for spending time on these Qs!
(1) Q is defiend as 1/(ωCgsRs) it is UNRELATED to either Lg or Ls while it is related to (Lg+Ls), and since I didn't chang the size of transistor, so Q is fixed. So...... do you still chose (4)? :)
(2) Yes, (2) is corrent , we can check this from fig.5.8 of shaeffer's PHD thesis. But (4) is also correct. This can be proved by
F= 1 +Rl/Rs + Rg/Rs + (γχ)/(αQ)*(ω0/ωT)
So when Q=Qopt, F = Fmin, and Q=1.5 in this case.
(3) Yes, I'm sorry for that i didn't make myself clearly. When power consumption is LARGE, the tolerance of Q is large, so there is acceptable difference between Q=2~8
So even the new correction post by Shaeffer in Jun, 2005 is Q=2.598, there is not to0 many difference between Q=4
(4) All the work Shaeffer done is not assumed to be input power matched, EXCEPT his constan Gm optimization. He assumed power matched condition to derive Gm. The Qopt under constant Gm optimizaion is 2.184(fixed to 1.5 @Jun.2005), it is not specified to be input power matched under contand Pd optimization where Q=3.781(fixed to 2.598 @Jun.2005)
I may be wrong, how you think?
if u change exchange the Lg and the Ls, need we modify the Cgs to keep WT*Ls=Rs? and hence Q changed, hah?
i agree with u that option 4 to Q2 is right, the equ31 of shaeffer's paper can show us, can i say that?
i think it is a precondition that the power is matched to Rs=50ohm, so, the Gm fixed and power fixed is based on the 50ohm matching condition.^_^
frankly speaking, i am not so sure about the understand to that "involved paper", and the paper written by the Korean is also confusing me a lot (some mistakes i think, but the analogous "comments and corrections" must be a long story to wait)!
BTW, if one is content with superficial understanding, he can use the conclusion of Q=4, the design based on it is reported successful and my exprience is "Q=4 based methodology is also qualified". hehe, maybe i am a lazy boy:D.
(1) So what if i did not modify Rs, and left the input interface unmatched? Maybe i should stare my condition more clearly, fix everything, fix size, fix current, fix Rs, only swap Lg and Ls, will noise factor F change? And please note that i did not assume ωTLs=50 in the initial case.
(2)umm....no, the derivation of Noise factor F did not assume ωTLs=Rs, could you please check this for me? Because I have read the whole document for a lot of time, and I dervied the equation by myself,too. Maybe i missed something, but I think the equation of F does not needs input mathced condiftion. At least I did not make such assumption while i derive the equation F.
The only equation that indicate input is matched is:
Gm=ωT/(2ω0Rs)
But this equatio is not used under power constrain optimization.
By the way, the Korea's noise factor's equation is strange.
(3) That's what I am tring to say, there is no too many difference if you set Q from 2 to 8. If the power consumption is large enough.
i am sorry to late reply since i am busy engaged in debuging my chip these days. the lna seems to be a good girl (my opinion, ^_^) but the mixer, so, i must spend a lot of time re-doing the simulation and think it through (u know it is a targh story, i am almostly crazy about it day and night)! so do u have an email via the "messages", maybe i can contact u when time is available (i'll send u mine), this topic is very interesting i think!
i am so sorry about the messing.
I'm sorry i take my words back. The Korean's paper does not assume Cgs to be resonant with (Lg+Ls), so the noise factor equ. is different to Shaeffer's.
hi supermen:
i want to join in your discussion, put forward my understanding, please correct me. thanks!
As the korean's theory(such as " cmos low-noise amplifier design optimization techniques"), matching condition includes two aspects. one is input power matching which comprise of real part and imaginary part, the orther is noise matchment which also comprise of real part and imaginary part. these two imaginary matching condition is approximately same, however, the real part matching condition of input power is wt*Ls=Rs, and the one of noise matching is only related to Width of M1, so the condition wt*Ls=50 is not affect noise matching as long as input network resonate at working frequency. shaeffer's theory is only approximately satisfy noise matching condition due to power constraint .so in Q1, F1=F2, even though i think it is not reasonable.
in Q2, i agree with answer(4) . i can't understand answer(2). how to increase power dissipation, while keep Q unchanged and fix wt.
i want to put forward my questions:
(1) fix power, there is a optimum width of transistor which make NF appear valley, is it right?
(2) fix bias conditon , sweep the width of M1, is there a same phenomenon happened?
(3) fix device dimension, sweep the Vgs, the NF will decrease all along untill arriving at minimum,then keep constant because wt reach saturation? or there is a optimum value, in other words , NF will appear a valley?
i am very interested in this subject, but very confused
Added after 4 minutes:
hi dsjomo
what do you mean " take your words back"?
Korean's nosie fator equation is not assumed input power matching?
Somebody has available the suggested paper:
Corrections to ?A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier?
Shaeffer, D.K. Lee, T.H.
Publication Date: June 2005
Thank you,
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