digital phase detector ghz
If you use the standard phase frequency detector design with 2 asynchron resetable registers and a AND for the reset path you need 90-130nm device to reach 6GHz. But I estimate that because of the delays the useable phase range is limited. So a classic multiplier should have a better performance. A combination of digital and analog PFD could give to best total performance. So use the digital PFD for integral loop part and the analog PFD for the proportional loop part. It is also possible to divide the reference and the frequency signal only for the digital PFD.
Do you want PFD in PLL to work for 6 GHz?
If so, why do you need such a high comparation frequency?
What exactly is working at 6 GHz? If it's the VCO, then persumably you have a loop divider to divide down to a comparison frequency. If you truly have a 6 GHz comparison frequency, then I would think that you will need an analog approach for a Phase Frequency detector, as the pulse width's and rise times strike me as pretty aggressive for digital circuitry.
Dave
Nobody will design such kind of PLL, unless it is for CDR purpose.
Clock synthesis will require reference clock from crystal. No crystal can generate high frequency to be compared in PFD.
If it is CDR PLL, mmm..., please use CML dff (if you use Alexander PFD) to run at that high clock rate.
Without divider you'll have many troubles with it. Instead, you can use divider to compare the signals and then pumps the current. In this case Phase Noise will be better by factor N dividing ratio.