DFF design for RF PLL

Anyone has info on actual design and layout of classical DFF to be used in high perfromance PLL ?
I'm mainly interested in actual layout tips ... if any.

Thnx,

nathan

what's the DFF?

I think the most logic is SCL.
search it in IEEE,you will many papers about it!

DFF = Dynamic Flip Flop

Basically it is generally abstracted as a D Flip Flop. If you cascade them, the flip flop provides for division of the input clock. The topologies can be of TSPC or SCL logic, hence when you do the layout it would be different.