multi-slot power profile

Hi

Anybody have idea about this correlation.
In 3GPP, for instance, it says 0 to 3 dB power reduction for
2 TX slots. Only some points I have in mind are,
1. To avoide too high PCB / phone temperature increase in time average.
2. To avoide PVT failure of multi-slot operation for some poor PA or poor
bypass capacity near PA with insufficient electical capacity supporting PA
to transmit enough power in short duration or transition.

Welcome ur thinking or feedback !

Regards,

Thougt about it.
I coudn′t find any possible explanation. The first thought was, how much data
had to be transmitted.
The explanation of higher temperaure makes sense, but how much is it anyway. Can
you give examples?

Greetings wheelbarrow

Added after 54 seconds:



I forgot, what is PVT?