linear range of PFD

Is there a normal value for the linear range for PFD over a 4*pi span, say 70% or 80%? Or is it strictly a relative term as long as it can satisfy the frequency acquizition time requirement? As far as I know, the closer to 4*pi the linear range, the faster the PLL can complete frequency acquizition, correct?

Besides, when simulating the combination of PFD/CP by sweeping the phase difference to check for dead zone, what should the CP output connected to? A ideal DC voltage source of 1/2* Vsupply? Or a capacitor? And when taking dft of the transient result, if the CP output settles into steady state after 100ns as opposed to after 200ns, does how fast CP output settles directly affect the settling time of the overall PLL? How are they related?

Appreciate any insight.