Help~~~~design AND gate in PFD....

I am now designing a DCVSL AND gate used in PFD. How much shoule the cross point of the differential output voltage curves be to drive the next stage's two input NMOSs ? When I adjust the W/L ratio of the PMOS and NMOS, I found that the crosspoint changed. It can be lower than the threshold voltage, near the threshold, near (Vdd+Vss)/2, or even larger. Which should i choose? I think when near threshold, there weill be the least time for the following two NMOSs on simultaneous.But if near (Vdd+Vss)/2, it seems symmetric....