frequency divider design

I am working on a 10G a dual modulus (128/129)frequency divider design for FS. It will be using SiGe bipolar topology. The spec is not finalized yet for phase noise and input senstivity of this circuit. I don't have much idea how they should be decided. Can any people give me some clue here? Thx!

if anyone has experience with pll and fs design, please shed some light on this... thx