pll testing

Hi, I am testing a PLL chip, it is not my design. That design has no constrain of speed and phase noise, actually the freuqncy is just several MHz. The designer has a transfer function when he designed the chip. Now I take over the testing. How can I test the PLL chip to verify the design is correct? Frequency step? What kind of testing should I perform? Thanks.

the lock state , check if the PLL is locked or not
then try to change the division ratio and see if the PLL is locked ot not

khouly

Hi, Let the PLL jump between two frequencies and see the PLL/VCO control voltage for over shoots and how long it takes to lock. Test the min and max frequency range and make sure it locks on both frequencies within the specified time. Measure with an spectrum analyzer the phase noise to see for strange things and have a look at the spurs next to the carrier.

regards,

Paul.

Thanks. The PLL locks in a very large range.
We planed to use a 3rd order loop filter when designing the PLL, however, when I am testing the chip, I can not find the right value of caps. so I just choose a 0.1uF Cap, which is the smallest Cap I have, and a resistor to make a 1st order lead-lag filter, it works. The locking range is prety large.

As I said before, we have no lock time constrain and phase noise spec. So what should I test next? :)

Do I need a function gen to create the freq jump? I am waiting for the new function gen to come, before that, how can I make a freq jump? Manully tune the signal gen?

You do not seem to understand the basics of control loops.

You want to insure that, over the entire range of divisor ratios and operating temperatures, the loop is stable. Otherwise, you can have big trouble in little china.

I like the idea (above) of watching the analog control voltage while you step from one frequency to the next. You are looking to see if the control voltage rings a lot (like the control loop is about to break into oscillations).

As far as randomly moving around values in the loop filter, you are playing with fire. If you do not know what you are doing, leave them as the original designer intended. If you are interested in learning what they do, you can try playing with one of the canned programs that people like National have on their website. Moving some capacitors/resistors will change the settling time. Moving others changes the inherent loop stability. The effects are often coupled to each other.

If you learn more about control loops, you are trying to insure that you have at least 45 degrees of "phase margin" (and 60 degrees is better) under all conditions with your RC choices.

I did freq step testing before, it settles quite well, I can count only 2 peaks, less than 4, which means my loop is quite stable. I know control loops and phase margin, they are very basic. My concern is, for PLL design, we use behavior model to get the loop transfer function as shown in the picture (PM 45 Deg, loop BW 1MHz). But after the chip come back, or even in tansistor level transient simulation, we can not measure/simulate the transfer function. It looks like the step response is the only way we can check the loop response (under damp, over damp or flat response). Besides freq step response and PN testing, what else do people do to characterize the PLL design?

I have another question, in calculating the filter component values, we need to know the output current of the PFD, a good example can be found in the National Semiconductor App Note of "An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump Phase-Locked Loops", but when we use the PFD as shown below, there is no fixed tail current, how can we design the loop filter? BTW, this simple structure works very well, I can see in my testing.

If I want to integrate the whole PLL including the loop filter, since component values chage a lot durring fabrication, the integrated loop filter may not work properly, how can I make a tunable passive loop filter on chip? Or is there other pratical way people do to ensure we have the flexibility to tune after the chip comes back? Thanks.

Hi, Use an external resistor to set your phase comparator current source !.

Paul.

PS: Did you design a complete PLL on chip ?..

Where should I connect the external resistor? The PFD output? But in that way the current will change according to the output voltage (of the resister terminal directely connects to the loop filter), so that the current is not fixed. So I guess we can use the voltage when the loop is locked, I call it Vfilter here, so the charge pump current should be (Vdd-Vfilter)/Rexternal when charge or Vfilter/Rexternal when discharge. Am I right?

Yes, I am planning to design the PLL on chip, any suggestion? Thanks