About divider structure

For a high frequency prescaler, we can choose Current Mode logic(CML) to realize high speed. But CML can't divide a low freqency sinewave signal such as 10MHz.
If I want to divide a signal about several Mega with CMOS process, What kind of structure can I choose?

static logic , or dynamic logic

khouly

You may try TPSC to build Master-slave DFF for the clock division.

CML could operate down to DC. It depend only on the detailed bias dimension in the dividing latch if you observe in simulation that it does not.

Otherwise CML is not energy efficient at low frequencies because the typical current scaling have limits.

But many products show that CML divider can only operate down to DC by suqare wave. Do you mean I can change the circuit parameters to make it down to DC by sinewave?

I do not know if you using an existing IC or want to design one. If the CML divider is for broadband purposes a slight mismatch in the latch avoid high frequency selfoscillation if the zero crossing slewrate is small.

I want to design a divider to divide the crystal oscillator output of 10MHz around. And do you mean I can realize it using the CML structure?What I really want to know is what structure is mostly used for this frequency?
Thanks.

Ok, what is used!

A low noise diffamp with a CMOS level converter.

Things are much easier if I know the background

How can they realize the function of dividing frequency?Related documents are preferred.I am a beginner in analog and RF, thanks for your helps.