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reference spurs

时间:04-10 整理:3721RD 点击:
can we estimate the reference spurs (Fcomp leakage at output of VCO) of a pLL?

Sure, but you need to know a fair amount of technical stuff about your system, like does the op-amp have an input offset current error, what is the open loop gain of the system at the spur frequency, how much time delay is in the system, etc.

Ok, suppose I have the critical parameters, what can I do?
Is there any formula or a tool for estimation of Spur?
I want to know that how much my design is good?
With this estimation, I want to know the effects of other things such as layout and
....
Please help

u can google pll design software
most pll software can help u do that

usually, the softwares simulate the loop caracteristics, they do not take details of PLL ICs, so the do not estimate reference leakage spur.
if you have a software that can simulate spurs, please let me know the name of it.

Analog Devices ADISimPLL can do it:

http://www.analog.com/en/DCDesignToo...%255F0,00.html

I've tried it myself and you can enter various (charge pump) parameters, not only loop filter, so spurs are simulated!

thanks that's good.
I saw it.
But only Analog Device ICs Can be simulated with this Software, Is'nt it?
if Not please tell me.

www.edaboard.com/viewtopic.php?p=166750#166750

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