How to improve P1dB in LNA design ?
I design a 0.13um LNA design , The Band is about 100MHz. Now I meet some questions about linearity (P1dB) . MY Design P1db is about -20dBm. But the specific is about -10dBm, How can I imporve it ? My design inlcude high ? low gain. Do I need to care the P1dB is the high /Low gian, Or just foucs on Low gain stage. Aother questions, If I want to do balun in the chip, the CS+ CG is only choice ? Thanks
hello,
P1dB is due to "i guess" other harmonic components whose effect will dec. the linearity and so to enhance the linearity i think u might dec. the gain , but maybe there is some other solution , anyway if u have gain margin u may dec. it
about the linearity of the LNA , is maily dependent on bias point of the gain "transisitor" , and adjusting this point will increase or decrease the 1 dB compression point , and for sure this will decrease the gain so u need to be carefull when u change the bias point and optimize it to get the best gain , and linarty
khouly
Dear khouly :
The Linearity is depand on Vod ,right ? My specific is 0.13um/1.2v/100M include balun . so that headroom is my point. I don't have large Vod to improve P1dB. If you decide it , which structrue do u select ? Thanks. I use CS+ CG have I tail current , the load is resistor. Thanks
do u have a degenration coil , it will increase ur 1 dB point
khouly
i have no experience with LNA's at all, but aren't there some active load topologies , it may help ur headroom
Dear khouly:
I don't use it, Because my LNA include balun, the LNA is differential input .
RF_P is ac couplr, RF_N is connect to gnd. I use CS+CG hace tail current do balun.
so that my structure is VDD-Resistor-NMOS-NMOS input and Itail current. My point is 1.2v dsign, The headroom Issue. So that the P1dB is not enough. Do u have any comment to solve this problem. Thanks
try to minimize the voltage doro on the trail device so u have a enough headrom to control the NMOS point , so u can get the 1dB comp point
khouly