simulink delta sigma frequency synthesizer
时间：04-10
整理：3721RD
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Having a problem with my simulation using Mathlab, Simulink.
Fractional input to delta sigma modulator is a DC value.
Output of the delta sigma modulator is a 4-bits wide output, which is fed into a 4 bits controller to manipulate the Multi Modulus Divider.
The simulated synthesized frequency output doesn't seems to work.
Any suggestions or advise is greatly appreciated.
The attached file in .mdl to simulate using Matlab Simulink is as follows.
Fractional input to delta sigma modulator is a DC value.
Output of the delta sigma modulator is a 4-bits wide output, which is fed into a 4 bits controller to manipulate the Multi Modulus Divider.
The simulated synthesized frequency output doesn't seems to work.
Any suggestions or advise is greatly appreciated.
The attached file in .mdl to simulate using Matlab Simulink is as follows.