How do you reduce PCB parasitics ?

Simple Question: How do you reduce PCB Parasitics or more importantly stop them and take them into account for microwave applications ? Modeling ? De-Embedding ? Material ?

Any books, thesis, ideas would be helpful.

For estimating pad capacitance you can just use the parallel-plate capacitor formula. Just add this into your simulation (toggle on and off) to see how much the circuit is affected. As frequencies go higher then this is more of a transmission line effect. To truly capture almost all the effects you must use microwave-design techniques where every component (with footprint) has well defined reference planes, and you know how it was measured. I'll plug Modelithics since they have a very nice CLR library with substrate dependant models and good reference planes at the footprints.

For instances where isolation is not a big concern you can just space metal at one substrate thickness away from transmission lines (when they are not too long) and not affect Z0 much. Now if coupling is an issue you can use EM simulation to get a feel on how closely you can space things. Don't need to simulate the whole structure, rather some test structures such as coupled lines. The Microwave Office EMEXTRACT feature is very handy for this as is Sonnet.

Using a thin PCB reduces coupling and via inductance, but increases pad capacitance. Choose a low Er material unless you need distributed elements in which case high Er will reduce size.

Thin pcb material may cause signal leakage at high frequency,say radio frequency.
but for general application, FR4 is enough. and almost every 3-D/2.5D simulator has FR4 model.

Paracitic Capacitance in PCB design is not remove-able. You can only minimize its effect to your design by adding "faraday shield". Please refer Analog Device's <<Analog Dialogue>>'s "Ask the Application Enginner - 21". The Link is as below:

http://www.analog.com/library/analog...ersary/21.html

You can leverage the faraday shiled idea for your RF design in handling this problem

Paracitic Capacitance in PCB design is not remove-able. You can only minimize its effect to your design by adding "faraday shield". Please refer Analog Device's <<Analog Dialogue>>'s "Ask the Application Enginner - 21". The Link is as below:

http://www.analog.com/library/analog...ersary/21.html

You can leverage the faraday shiled idea for your RF design in handling this problem

The answer is to put all components as close together as you can. And get a PCB with the lowest dielectric constant you can afford, ie 2.2. Like the guy above said, you can only minimize them.

The latest book from Artech House

"Essentials of RF and Microwave Grounding" By Eric Holzman

where we can find it?

Buy the book, support the author!

as for my opinion -- just model the parasitics. If you make this part of your design flow then you'll rarely be surprised by them. There just aren't that many shortcuts in life....