Broadband bias circuits
I need to design a bias circuits which can reject RF from going to the DC supply without cause niticeable insertion loss at the signal line. The operating frequency is from 1 MHz to 3 GHz. Can anyone suggests some idea how this can be done? Thank you.
Linda.
Use the maximum coil value which has higher resonance frequency smaller than 3GHz and then a low ESR capacitors parallel starts from few picofarads to few hundred nanofarads.
Small capacitors will act as decoupling caps. for higher frequencies, higher values will function for lower frequencies..
A Bias Tee consists of them..
Hi
If you are looking for a choke that works from 1M to all the way upto 3G- then one way I have seen people do that is connecting inductors in series such that each one of them work in separate bands (min impedance). To elaborate, lets say you have three inductors (L1, L2, L3) in series L1 works(Z>500say) at low freq, L2 in the middle of the band and L3 at the highest freq.
Usually a capacitor to ground, is added at the end to decouple. (I suspect it plays some role in compensating for L flatness as well).
Hope it was useful.
The previous reply is a common way for your application. Additional measure you should take is to put each stage of the inductors in parallel with a resistor which is necessary to flatten the final S21 response. RF simulation tools should be used for optimization. Be prepared for about half a dB loss. If go beyond 3G, EM simulation is necessary for this kind of structure. You should use more than on decouple cap also.
Good luck
Thank you guys or the help. It works perfectly.
Linda.
I am wondering why put several inductors in series instead of using one inductor only?
Thanks a lot
Hi
To rfsurfer
Why do we need to put a resistor in parallel to an inductor. I have seen it in a datasheet as well.....do not reslly understand?
Could you explain
you should pick up a book named--broad amplifier design
you question explained well in the book
many design examples and measurement.
good luck.
Hi wjnbry
who has written the book?
regards
"Why do we need to put a resistor in parallel to an inductor. I have seen it in a datasheet as well.....do not reslly understand?"
inductances (lumped) have resonances too. So a parallel resistor damps or reduces Q of the resonance formed by inductance and its parasitic capacitances...
Hi
Do I understand it correct, when BW=Fo/Q. So we increase the bandwidth by introducing "loss" in the inductor by adding a resistor or what? But dont we increase the Q by adding a parallel resistor instead of placing it in series?
Maybe I get it now......For a parallel circuit Q=Rp/omega*L. So if we add a second resistor in parallel we decrease Rp, which in turn decrese our Q and in the end increase the bandwidth.....right?
Regards
Yes. It's mainly for damping. Overall frequency optimization should be done with EDA tools.