A question about phase-selecting divider...

I am now designing a divided-by-2.5 prescaler using phase-selecting technique. So first a divided-by-2 prescaler is designed with CML circuits and then the four quadrature signals are selected by a MUX to the output. The question is how to design the control logic of the MUX. I know the MUX have to choose the signal which is 90 degree delayed with respect to the present signal. But when and how does the swiching happen?
I read some papers about this topic but none of them told me how to control the MUX. Can you please explain this more detaily to me or recommend some papers on my question.
Thank you guys.

You may refer to Perrott's thesis:
http://www-mtl.mit.edu/~perrott/pages/thesis.pdf