jitter spec for DAC clock?

I need to specify the clock jitter requirement for baseband DAC which transmits 50 MHz BW signal (centered around zero frequency) it is 16 bit DAC. If someone could help me to find some equations to calculate the clock jitter spec. It is of course dependent on the desired SNR but should I use 25 MHz as highest frequency in jitter calculations (+/-25MHz BW around xero freq)?

Thanks in advance

How do you propose getting a negative frequency out of a DAC? Commonly, this is done by having 2 channels in quadrature.

In your case, 25 MHz would be an appropriate frequency for the highest signal frequency. You clock frequency will be greater than 50 MHz. There is a nice application note on the Analog devices web page that talks about clock jitter and SNR, which shouldn't be to hard to find.

Dave

Excatly, I have dual DAC and the "negative freq" is coming since the other output is for in-phase signal and the other for quadrature phase component. This is feeding a IQ modulator

1) you need to know the required SNR for demodulating your signal. (say - X)
2) Allocate the degradations due to other components ( mixer, buffer, PA, transmission loss .... ) - Y
3) SNR required at the DAC out = X + Y
4) SNR DAC out = 6.0N + 1.02 - DAC Errors
5) So u calculate dac errors = Non linearity + Jitter
6) You can look into ADIs website for the more details

hope this helps
brm