Problem in designing PLL [hlp]

Hello Everyone;
Suppose that in designing a PLL, maximum output voltage of charge pump is about 6V. But the VCO tuning voltage is up to 14V. How we can design the PLL?

it is a hard problem , i think u should check to see another VCO

khouly

Khouly wrote:
.

Have you any suggestion for 800-1400MHz VCO with tuning voltage of less than 6V?

I amnot sure what you are trying to say. If the only VCO you can find has a 14 V tuning range, you are going to need an op amp to provide DC gain.

If you do not have a 18 volt power supply to power the op amp, you are going to have to provide some sort of switching regulator to step up the voltage.


This is precisely why some VCO's use hyper abrupt tuning varactors, so you get almost all of the frequency change in the first 4 or 5 volts of tuning.

There are numerous app notes on active loop filter design. You should be able to find them at national or analog. An active loop filter basically uses an opamp to amplify the loop filter voltage.

There are too many design elements to list here, but an active loop filter with an opamp is the standard way to handle CP/Kv mismatch.

C

if u will use active loop filter , u need a high supply as well , and this will be a high power consumption

there are now oscillators working in the range of 5 and 6 volts

http://www.minicircuits.com/products/vco_sm_5v.html

khouly

U can design ur PLL using the WEBENCH tool it is almost perfect. U can find this tool on national semiconductor website.
Good Luck

why not can i open the address www.minicircuits.com/products/vco_sm_5v.html

also the ADsim PLL from www.analog.com , is great , but it is fo thier PLL's

khouly