Problem with output of conventional CML divider

hi
Iam doing the high freq divider (/2) for the first time. i just simulated the conventional CML divider (/2) with 5G input freq. To my surprise the output freq is 700M. I dont under stand why this is happening.
It has to give 2.5G.
Can any one explain this?

Thanks.

did u check the amplitude of this signal ?

what type of simulation u used , transient , or HB engine

khouly

I found the mistake.
I was using big transistors while doing sampling and holding stage. this is why the input txs are not able
very fast. when i reduce the sizes, evry thing is fine.......