CMOS PA class definition
Another problem: the Vth should be obtained from model documents or DC operating points? Thank you.
The A B C classes were defined in the days of valves/tubes and relate to how much of the sine wave cycle the device draws current.
A is all 360 degrees, B is 180 degrees, and C is less than 180 degrees.
Later AB was classified as between 180 and 360. AB1 was when there was no grid current flow and AB2 was when there was grid current flow.
When these are applied to transistor circuits it is only an approximation.
What is the definition of grid current?
In valves the control grid was usually biased negative with respect to the cathode. Even then anode current flowed.
The signal swing was added to the bias. If the total was positive some of the electrons from the cathode would be attracted to the grid and flow to the outside circuit.
Thank you, flatulent.
Do you know any other forum focusing on RF CMOS design? Many phenomina confused me in the design of CMOS PA.
In transitioning to transistors a whole new set of problems exists.
One problem with BJT amplifiers is that they have limited base drive power requirements and limitations.
In the early days of BJT RF amplifiers the transistors could not withstand class C conditions and all of them really operated in class A to B conditions and would be damaged with class C conditions.
Other EDA board members have noted that more modern BJT transistors will operate in class C without damage.
MOS transistors can operate in class C conditions. Examine the data sheets for the details.
Valve class C devices could operate with efficiencies of 80% while transistors cannot meet these conditions unless operated in class E. Class E conditions only operate with constant envelope modulation formats which are rarely used today.
GMSK was the last constant envelope modulation format used. OFDM is a more modern format which requires more linear conditions.
Flatulent, first, I would like to thank you for your quick reply.
The PA I am working on is integrated with other parts, such as PLL and receiver, on one chip. And the job is based on 0.25um CMOS process.
The modulation method is FSK. The PA should deliver a small power, about 8dBm, to the antenna. The power should be controlled with 3-dB step.
With this relatively low level of power any amplifier class will work unless you have unusually stringent battery life requirements.
With less than 10 mW of output even 30% class A amplifiers will draw less than 30 mW of DC power from your battery.
Actually CMOS PA in A mode is difficult to reach the efficiency of 30%. Most of them can only reach 20%.
So I make the output stage in AB mode and pre-amplifier broadband stage.
A problem: the specified frequency is 433MHz, but the choke of 33nH inductor with best mathcing(obtained from loadpull simulation) is sufficient to provide enough power. The output power changes little with increased choke value.
Do you have any explain on this phenominon?
In CMOS PA design one trick that could be done is to use multistage output L networks, to decrease the insertion loss and improving indirectly the efficiency.
Multistage L match may have lower insertion loss if the reactive component or components have low Q, even though the impedance transformation ratio is not high. The loaded Q of each stage should be the same.
A good simulation should be done to find the optimal number of stages.
How to define the Q value of reactive component?
You have to go back to the basics.
Read Bowick?s ?RF Circuit Design? and you will find the answer:
https://www.edaboard.com/viewtopic.php?t=60223
You could just use the NFET and go class E if your signal has a constant envelope.
But I need to control the output power by 3dB per setp. Thus, the class E needs a DC-DC converter to control the power. May I use class C to realize it?
Class C will have the same problem. You other option is to use a linear class and vary the drive.
I have found two method to control the power: vary the output-stage size; vary the preamplifier driver level. Which one is better?