about the disign process of pll

hi!
i am a freshman in pll design.i have built the phase domain model and voltage domain model with simulink,and also a voltage domain model with veriloga.however,all these models do not refer to noise.in my opinion,it is difficult to bulid. i basicly konw what cause noise.and now i can go ahead to design the transistor level circuits?
give me some advice!thanks a lot

u need to tune the top level system parameters and check the performance of the PLL , like changing the ICP , and check the settling time , and the phase margin and so on

then u can begin circuit design by knowing each block in the PLL spec's , u can begin with the PFD , and optimize it so u can minimize the dead zone , also the charge pump and try to make it symmetric to minimize the mismatch , then the VCO which require alot of tuning and many design steps to get the required tuning characteristics and also phase noise
then u have the divider design for best speed and power consumpssion performance

khouly

thank khouly!
i basiclly complete what u said.

great , and good for u

khouly

I will begin to do as khouly had said.

thank you