RFIC design in sleep mode? How could it design?

Dear all,

For the RFIC design, how could I make the circuit block in sleep mode (low current consumption mode). My friend told me that I could set the input bias voltage to zero volt. Is this method always use in commenical product? Otherwise, what typical method will be used? Moreover, how could it implement?

thanks

wccheng

ya in commercial products it is necessay to have more battery life
to get this wacth dog or sleep mode is available that wakes only if any emergency is present

In CMOS or BiCMOS RFIC design the power down mode is a typical design practice. In each circuit, each node is controlled (with CMOS small switches) in order to assure that the circuit goes properly in power down.
I hope it can help.
Mazz

usually in the RFIC to make the TX and RX in a sleep mode , the regulator of the block is turned on and off , so it control the status of it

khouly