How to measure input impedance of MC12179 frequency synthesizer for PLL design?

Hi
I am designing PLL oscillator. I intend to use the MC12179 frquency synthezier, In the datasheet they five us the input impedance( real and imagine impedance) by grapth. But in order to simulate in ADS, how to get this one. I have measured the input impedance by measureing the S11 of the Fin pin, but only the imaginary is look the same like in datasheet, the real part is less than 10 Ohm comparing to that of datasheet. ( I measure by with and without power supplying for the chip, crystal syppling,.. e.g. measuring while the chip in circuit-I take the circuit of LNB and try to analyze everyting and then simulate and then redesign-) So I did not believe in the measuring result.
I think we must have this input impedance in order to designing matching circuit,..Do you guys think so?

At what level did you measure S11? The specified input level range for Fin is 0.2 to 1.0 Vpp. Did you measure S11 using the specfied 1000 pF DC-blocking capacitor? My experience from using this device is that matching is not critical, as long as you can achieve the specified input voltage level.

http://f5ad.free.fr/Docs_Composants/MC12179.pdf

Did the MC12179 have an Application note? Some times they will
give you a circuit to test their device.

Also look at Fig 17 in the Link VSWR gave, 10 Ω is a reasonable
Impedance, depending on what frequency you're running at.

THank you.
I think impedance matching is not important too.