RF CMOS power cell layout

Now I'm involving some CMOS PA design, adn when I design CMOS power cell, when I use the tranmission line mode (ADS), everything looks like OK, but when I repalce this ADS lines with EM simulations, I found that the gain distorted a lot becasue of gate line, but drain line will not be affected, I utilize the DOngbu 013 um model, but this case will not happen on TSMC018um, who can expalin something? thanks a lot.


Besides, I found that if I set the conductivity of substrate=0, the gain will not distort and is similaor to ADS result