Dynamic Load Line (Medium Power Amplifier)

Hi,
In my amplifier design I've simulated the dynamic load lines at different input power levels, 0dBm and 10dBm (both at 4GHz).
My doubt is, with Pin=10dBm, the DLL obtained has a distorted shape at both ends and reaches more than 8V (Vds), beyond the Vds Absolute Maximum Rating that the FPD6836 datasheet says.
Does this mean that the amplifier will break?

Thanks

Well, it might be. I think there is another plot showing the maximum rating of the transistor. it will shade the area of safe region in the V-I curve.