Response of the TLINE for different frequencies and lengths

I agree that the relation between electrical length and input impedance are presented correctly in the diagrams. You should be able to see in in a correct simulation setup. Unfortunately you neither show your simulation setup nor the results, which answers do you expect?

In the short circuit case, as I increase the length when 0<length<lambda/4, I expected to see inductive behavior and lambda/4<length<lambda/2, I expected to see capacitive behavior. And the same behavior should repeat again beyond lambda/2

In the open circuit case, as I increase the length when 0<length<lambda/4, I expected to see capacitive behavior and lambda/4<length<lambda/2, I expected to see inductive behavior.

I attached my test setup and results

You are sweeping "freq" variable ? If it's so, you're doing a mistake because freq is not a variable for Cadence Spectre..
Instead, you should fix the frequency in s-parameters simulation in Spectre ( single point) then change the Line Length.
Also, look at Zm ( Port Input Impedance ) instead of s-parameters.

Exactly I did the same but you gave me one idea, I was not sweeping the frequency parameter in the TLINE. Should I need to do that to get its response against frequency or is sweeping the frequency in s-parameter simulation enough?

What exactly happens when we do s-parameter simulation, does it over write all other frequency variables in the schematic (in this case frequency parameter in TLINE component)?

In fact, it's more comfortable doing this test in ADS.Cadence Spectre is not so good for this type plottings.

Beautiful. I am not really good with ADS, as I never worked on it. Well, now I will try it in ADS.

Both 1 and 2 are possible in any simulator.
Simply still you can not understand parameters of tline.

Yes, for sure, I still don't understand not only about tline but also many other things. That's why I am here to learn from experts like you.

Don't feed the troll.



No, the frequency + phase delay in TLINE is only another way to specify the line length. So this should be constant during your frequency sweep.

I use Synopsys HSPICE from Cadence ADE.
You may use ".LIN Analysis" instead of ".AC Analysis".

"test_circuitslave_1.spi"

** Generated for: hspiceD
** Generated on: Jun 17 11:47:47 2019
** Design library name: My_RFDE_Test
** Design cell name: test_circuitslave
** Design view name: schematic
.PARAM f0=1G nl0=0.25

.PROBE AC
+    I(v1) IP(v1)
+    I(v0) IP(v0)
.AC LIN 1001 1e-3 4e9

.TEMP 25.0
.OPTION
+    ACCURATE
+    ACOUT=0
+    LIST=3
+    ARTIST=2
+    INGOLD=2
+    INTERP
+    METHOD=GEAR
+    NOMOD
+    PARHIER=LOCAL
+    PROBE
+    PSF=2
+    RUNLVL=6

** Library name: My_RFDE_Test
** Cell name: test_circuitslave
** View name: schematic
t1 net03 0 net02 0 ZO=50 F=f0 NL=nl0 IC=0 , 0 , 0 , 0
t0 net08 0 0 0 ZO=50 F=f0 NL=nl0 IC=0 , 0 , 0 , 0
v1 net03 0 AC 1
v0 net08 0 AC 1
.END

simulator( 'hspiceD )
design(	"/AHO/simulation/test_circuitslave/hspiceD/schematic/netlist/netlist" )
resultsDir( "/AHO/simulation/test_circuitslave/hspiceD/schematic" )
analysis('ac ?sweepType "linear"  ?numPoints "1001"  ?fstart "1e-3"  	?fstop "4G"  ?points "1G"  )
desVar(	  "f0" 1G	)
desVar(	  "NL0" 0.25	)
option(	'TEMPDC  "25.0" )
save( 'i "/V0/PLUS" "/V1/PLUS" )
temp( 25.0 ) 
run()

Xin_short = imag((-1 / getData("/i(v0)" ?result "frequencySweep")))
Xin_open = imag((-1 / getData("/i(v1)" ?result "frequencySweep")))

plot( Xin_short ?expr '( "Xin_short" ) )
plot( Xin_open ?expr '( "Xin_open" ) )

I used Cadence Spectre from Cadence ADE.
You may use "sp Analysis" instead of "ac Analysis".

"test_circuitslave_2.scs"

// Generated for: spectre
// Generated on: Jun 17 11:59:19 2019
// Design library name: My_RFDE_Test
// Design cell name: test_circuitslave
// Design view name: schematic
simulator lang=spectre
global 0
parameters f0=1G NL0=0.25

// Library name: My_RFDE_Test
// Cell name: test_circuitslave
// View name: schematic
T1 (net03 0 net02 0) tline z0=50 f=f0 nl=NL0
T0 (net08 0 0 0) tline z0=50 f=f0 nl=NL0
V1 (net03 0) vsource mag=1 type=dc
V0 (net08 0) vsource mag=1 type=dc
simulatorOptions options psfversion="1.1.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=25.0 tnom=25.0 scalem=1.0 scale=1.0 gmin=1e-12 \
    rforce=1 maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
    sensfile="../psf/sens.output" checklimitdest=psf 
ac ac freq=1G param=NL0 start=1e-3 stop=1 lin=1001 save=all \
    annotate=status 
save V0:p V1:p 
saveOptions options save=selected saveahdlvars=all

simulator( 'spectre )
design(	"/AHO/simulation/test_circuitslave/spectre/schematic/netlist/netlist" )
resultsDir( "/AHO/simulation/test_circuitslave/spectre/schematic" )
analysis('ac ?freq "1G"  ?param "NL0"  ?start "1e-3"  	?stop "1"  ?lin "1001"  ?dec ""  )
desVar(	  "f0" 1G	)
desVar(	  "NL0" 0.25	)
envOption('analysisOrder  list("ac") 
)
save( 'i "/V0/PLUS" "/V1/PLUS" )
temp( 25.0 ) 
run()

Xin_short = imag((-1 / getData("/V0/PLUS" ?result "ac")))
Xin_open = imag((-1 / getData("/V1/PLUS" ?result "ac")))

plot( Xin_short ?expr '( "Xin_short" ) )
plot( Xin_open ?expr '( "Xin_open" ) )

You are fantastic. Which editior do you use to write these codes. Also does connecting to "NoConn" instance means it is open circuited?

What do you want to mean ?
I don?t use any editor.
Do you surely understand Cadence ADE ?
Can you understand netlist ?

No.
It is not circuit. No more than symbol.
Surely see netlist.

As pet T1 (net03 0 net02 0), net02 is connected to T1 on one side. Where is the other side of net02 connected?. In the image you added, it is connected to "NoConn" instance. How did you get that? does connecting a net to NoConn also mean leaving it as open?

Nothing.

What do you want to mean ?

"basic/NoConn" is a symbol, that's all.

Compare Views of "analogLib/res" and "basic/NoConn".
And confirm cell property "nlAction" of "basic/NoConn".

Then consider and learn by yourself.