PLL lock time [hlp]

hello
is there any way for calculating lock time of a PLL in the design process?

As far as I know,the setting time can be affected by the gain of PFD

Hi

I attach a simple papers vs example to calculate LPF and of course lock time, please review.

David

hello
what's about a hybrid PLL (using DDS)?

The lock-time is easy to calculate:

With good accuracy it is simply: TL≈2*Pi/ωn
(ωn=loop natural frequency)

But realize that the lock-time is defined with the assumption that lock-in occurs within one beat-period. With other words: The frequency displacement is within the lock range.

If you know the bandwidth of you loop filter,
For example 100KHz.
So the lock time will be close to 1/100K=10uS.
But the lock time will be affected by the initial dc level.

just some reference for you!
with LPF BW=100K,not too bad phase margin,Locktime can be reached 60us.

with LPF BW=200K,not too bad phase margin,Locktime can be reached 40us.

Why?This is your experence?
But it is not match with the theory！

Why?This is your experence?
But it is not match with the theory！