Discrepency between CMOS VCO simulation and measurment

Hi,

I designed a VCO in 65nm CMOS and the measurment results don't match the simulation. Any ideas?

Thanks

Hi mbyoussef,
What do you mean by the measurment results don't match the simulation ?
Did you fabricated the chip to pick measurements and compare them for simulation ?
Btw, that's due to the process.

there are alot of reasons

1) process variation "but u should in the design cycle run monte carlo and check process corners"

2) non idealties in measurments and loading effects

3) what about the buffering of the VCO " every VCO need to be buffered"

Khouly

I never have seen simulation results which could "match" the measurements.
This is quite normal and logical. However, in this context the most important information is missing: What kind of discrepancy and how large is it ?

LvW

yeah there is some discrepancy between measurment and smiulation but at least there is analogy and coherence between them.

Khouly

Do you extract the parasitic RC of it.
It should be different because there is so much parasitic.
But this is also detemined by your layout skill.

Besides, you know capacitor and MOS will change more than 10% with process.
So what is the diffenence?

Thank you all.

I wasn't accurately modeling the caps in the design. Now the simulations somehow match match the measurements

Added after 12 seconds:

Thank you all.

I wasn't accurately modeling the caps in the design. Now the simulations somehow match match the measurements

good to hear mbyoussef

khouly