some questions about PLL

Ask for the general causes and solutions for loss of lock within a PLL circuit in low-temperature, thanks.

Hi,
You have to know that the VCO characteristic Freq=f(Vtune) shifts from High to low when the temperature decreases (the slope remain approximatively the same). As a consequency the margin of loking of the PLL changes.

The de-tuning of your Reference Crystal or VCO Varactor, any extra Gain in the VCO.

Try Google.

Reasons:
1) you exceeded the voltage tuning range that your charge pump/op amp can provide while maintaining lock
2) The VCO stopped oscillating at cold
3) Something is an intermittent contact, and it opens up cold (like a poor solder joint under the PLL chip)
4) the RF power into the PLL chip dips when cold, and the counter becomes unstable
5) some sort of oscillation in the op amp or voltage regulator cold (a long shot)
6) your reference frequency stops oscillating, or droops in power cold.

Thanks for all your suggestions, I found this problem is loop bandwidth-related and it can be improved when the loop parameters reseted.