maximum width in tsmc 0.18um process

hi all,

what is the maximum width that we can use in tsmc 180nm process..

as per the design equation(thomas lee's book) i got some 437um as width, but ads is giving an error that maximum width is 100um

even after using fingers it comes around 320um..

how to get around this prob or am i missing something here?

please help me out..

thank u all....

Hi Kumarn,
You will get exact number from TSMC PDK manual. see Thomas Lee took width of 437 um for 0.25 or 0.6 um process for which he has design CMOS LNA.

But, your process is 0.18 um so, there must be some maximum limit which you can come to know from Design PDK manual.