Effect of number of fingers and width of a transistor on Efficiency and power gain

Hi, Say total gate width = constant = number of fingers*finger width. Does it impact Efficiency and power gain in a power amplifier, how I chose the number of fingers and finger width. More fingers and small finger width or less fingers and large finger width?

Trade off between Rin, Cin and Cout.

I need more information on this, someone told me If I choose more gate width and less number of fingers it increases parasitics. But I have never read much about these tradeoff. May be some documentation or references would help

Read Razavi’s CMOS Analog text book, not RF microelectronics.

This theory is for GaN but the provided information can be applied to other processes:
https://publikationen.bibliothek.kit...021579/1761764

So it says that If the number of fingers is more the MSG/MAG will decrease as the external capacitance Cgd increases.
and PAE=(Pout/Pdc)*(1-1/G) so as G decreases PAE also decreases. In conclusion, both PAE and gain decrease with increase in the number of fingers.

Can you also say Effect of number of multipliers of a transistor on Efficiency and power gain

There have been quiet a few publications on this, and I request you to look up the work done by Patrick Reynaert on this.

Efficiency depends on a lot of things and its hard to directly link to transistor parameters directly. PAE depends on power gain (Gp) unlike drain efficiency. (When you are talking about PAs mention what type of efficiency). So higher gain (without increasing DC power) would automatically lead to better efficiency.

Now the absolute maximum gain that you can get is a function of the fmax of your device. There are two main "gain" killers --> gate resistance and Cgd. Cgd can be taken care of by neutralization.
Gate resistance has several components:
1. Interconnect resistance arising from connecting the gate terminals of different fingers (the more number of fingers you have --> longer the interconnection has to be --> higher gate resistance)
2. The horizontal component of the gate resistance which is due to the silicide (less wide gate -- lesser length of the silicide --smaller resistance)
3. The vertical component of the gate resistance which is the resistance through the poly-Si or metal bulk of the gate (basically the part that contacts the SiO2 below). [Wachnick, IEEE 2013]
4. Non-quasi component of the gate resistance (inversely proportional to the gate width)

So there are a lot of components and each one impacts the gate resistance in a different way. And therefore, there is a sweet optimal somewhere in between. You need to layout your transistors and then do a PEX followed by a simulation to find out what works for you. There is no one answer for you.

Good luck!



The conclusion is true if and only if Cgd is the one affecting your gain. People use differential PAs to get rid of this nasty Cgd (plus a host of other advantages).



Multipliers increase the device area. You will need more interconnection, and your gate resistance can negatively impact you.