Re : Triple well in tsmc .18u
时间：04-08
整理：3721RD
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Hi,
I knew that in tsmc .18u process has triple well P,N,P. => By draw PNP guard ring in
layout. And then to take account to design for simulation. Then there are TWO diode such as : DNW diode and PSUB diode in design that matching parameter to layout side.
Could you draw or describe : how these diode connect.Please using of P+ and N+ for that .
Thanks,
Phuong
I knew that in tsmc .18u process has triple well P,N,P. => By draw PNP guard ring in
layout. And then to take account to design for simulation. Then there are TWO diode such as : DNW diode and PSUB diode in design that matching parameter to layout side.
Could you draw or describe : how these diode connect.Please using of P+ and N+ for that .
Thanks,
Phuong