How can the PLL feedback divider N=10?
I have some ADF4107 chips in my hand. But I found that the dual modulus PLL , when it comes to feedback divider (or as the rf divider ) N=B*P+A, needs B>=A. The modul is P=8, then How can I realize N=10, 11, 12, 13 ,14, 15? My PFD frequency is about 25 MHz. So just change it from 25MHz to 6.25MHz won't work cause the active loop filter will be a terrible task for me.
I am not sure exactly what you are asking, but there are bands of divisor ratios that are not allowed in dual modulus dividers. The math simply does not work out. You have to design your system to work around these. It is sometimes not that clear exactly which divisor ratios are not allowed, but typically the simulation programs provided by the manufacturer will not allow you to force the divisor into those "not allowed" conditions.
You can try lower phase detection comparison frequencies, change the clock frequency, etc, to juggle the numbers around to use a chip. Sometimes you have to abandon a chip for another one to accomplish your system design.
Are you sure ?
Don't you mean P>=A ?
Actually I thing you are wrong in that point. So for by 10 division choose B=1 and A=2 and that's all.
I know there are some single modul PLL, such as ADF4007. However, they can only work for N=8*k, where K is an integer. I can't lower phase detection, cause there is swithcing speed demands. My loop has to be 1MHz. Why there is not any PLL chips whose N divider just is the same as R divider?
Added after 2 minutes:
Are you sure ?
Don't you mean P>=A ?
Actually I thing you are wrong in that point. So for by 10 division choose B=1 and A=2 and that's all.
