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When using a MMIC or transistors above ~100 MHz, using a "wire" is not a good idea.
At e.g. 433 MHz, using a stripline or coaxial devices and interconnects works best. When I need to interconnect MMICs , I use a microstrip on FR-4 Teflon substrate, 50-Ohm sections. To connect connectors or to make interconnects, I use with a good success short sections of thin sheet; e.g. 0.05 mm thick and 1.0 mm wide.
I use such interconnects for up to ~5...6 GHz without problems. A round wire would rather behave like a lossy inductance- my "flat" wire looks pretty lossless.
I learned it from the method how MMIC dies are connected- either several gold wires are used in parallel, or, gold flat strips. It works in very short links to > 50 GHz.

It really depends on the ratio of line length and wavelength. My understanding is that we are talking about on-chip transmission lines, where the length of lines is on the order of some 100μm at a wavelength of 700mm, so we have l/lambda on the order of 1/1000.

Below is the impedance tranformation by a line with characteristic impedance Z0. You can see that for small l/lambda values, Zin ~ Zload no matter what the line impedance is. The tan (2*pi*l/lambda) part is so small that it is not relevant in that case. Transmission line effects start to show when the line length become significant compared to the wave length -> tan () no longer small.

When you route your signal lines, don't forget the ground return. Both are equally important. Sounds trivial, but when I see layouts of RF circuits for EM modelling, many people seem to focus on the signal line and forget about the return path.

If your circuit is sensitive to magnetic coupling from other parts of the circuit, keep signal and ground not too far away (= avoid magnetic coupling loops).

For the line, the transmission line effects are not a big issue on chip at 433MHz, but you should check the ohmic resistance of the line because the cross sections are so small. Narrow lines on thin metal layers can easily have some Ohm of resistance. You want to keep the resistance small, so avoid very narrow lines on thin metal layers.

It really depends on the ratio of line length and wavelength. My understanding is that we are talking about on-chip transmission lines, where the length of lines is on the order of some 100μm at a wavelength of 700mm, so we have l/lambda on the order of 1/1000.

Below is the impedance tranformation by a line with characteristic impedance Z0. You can see that for small l/lambda values, Zin ~ Zload no matter what the line impedance is. The tan (2*pi*l/lambda) part is so small that it is not relevant in that case. Transmission line effects start to show when the line length become significant compared to the wave length -> tan () no longer small. It is an on-chip RF integrated circuit using .13um process.

So does it mean transmission line can be ignored in my case because of the ratio of wire length and wavelength?

What about the width of the RF signal wires? When I draw the the wires in Cadence layout window, I do need to calculate the width of the wires? Any suggestion besides looking into the design kit manual?

I am not an RFIC designer, but I do EM analysis of RFIC components and interconnects. From my perspective, the width of your line is not critical (at least not for RF reasons). Something on the order of 20μm should be fine, so that the ohmic losses are small.

edit: changed value to 20μm width

When you route your signal lines, don't forget the ground return. Both are equally important. Sounds trivial, but when I see layouts of RF circuits for EM modelling, many people seem to focus on the signal line and forget about the return path.

If your circuit is sensitive to magnetic coupling from other parts of the circuit, keep signal and ground not too far away (= avoid magnetic coupling loops).

For the line, the transmission line effects are not a big issue on chip at 433MHz, but you should check the ohmic resistance of the line because the cross sections are so small. Narrow lines on thin metal layers can easily have some Ohm of resistance. You want to keep the resistance small, so avoid very narrow lines on thin metal layers. Thank you for the suggestion.

Besides consideration on resistance of the thin wire, how do the width and depth of the thin wires affect avoiding the magnetic coupling effects of the wires ? Thanks![/size]

[size=2]Added after 4 minutes:

I am not an RFIC designer, but I do EM analysis of RFIC components and interconnects. From my perspective, the width of your line is not critical (at least not for RF reasons). Something on the order of 50-100μm should be fine, so that the ohmic losses are small. Thanks for the reply. That makes sense to me.

Another question is how I can roughly calculate the length of thin wires within the RF IC chip? I am curious how you got 100 um length for the thin wires.

These are two different aspects. I just mentioned the magnetic coupling to indicate the routing and placement of lines should be done with care, even if the line impedance is not an issue. If your total loop of current and return path spans a large area, it will be more sensitive to magnetic coupling.

The "some 100 μm" was just an estimate of a line length between functional blocks. Maybe 500μm or so? But you know your layout size and should have an idea about the maximum line length.

Note that I had mistake in my previous post on the line width. The width would be more like 20μm or so, not 50-100μm.

Thank you very much!

Since the ratio of the wire length and wave length is somewhat like 1:1000, so transmission line design is not that important in the RF integrated circuit design. Does it mean that if transmission line is taken into consideration, it is more beneficial to RF design (more accurate)?

Another important thing. Is there any learning materials or resources (books/articles) you recommend for me to get more familiar with RF layout design rules (on-chip level)? Thank you very much. This is very urgent and important to a project I am doing.

In your case, just follow the rules for "good analog design". The additional RF aspects do not make a difference because of the size/wavelength ratio. Your elements can be considered lumped. RF aspects will start to matter when you do RFIC design at much higher frequencies, and the elements must be considered distributed (e.g. current on the wire can no longer be considered the same at all locations).

My personal background is RF/microwave, not chip design, so the RF books that we used in our education had a different focus (design of distrubuted circuits from transmission lines). I did some web search now for you, but did not find something that matches exactly what you need. This one gives the "bigger picture" to understand when transmission line concepts must be applied:

Class06 Transmission Line Basics

When you calculate the wavelength of the RF signal, did you just use lambda= speed of light (299,792,458 m/sec) / frequency ?

Yes, this is the wavelength in air. To be precise, we also need to include the effective permittivity of the dielectric. If we have SiO2 dielectric all around, that decreases the wavelength by SQRT(epsilon) = SQRT (4.2)

lambda = c/(f*SQRT(eeff)).

What about simulation in AWR? sharethewell wants to find out effect of line width on his 433 RF circuit. Cant we setup and simulate a circuit in AWR that shows this effect instead of making calculation? If the effect is too small to observe, lets make it 2.4 GHz or 10 GHz. I m beginner in AWR and sharethwell's points interest me too. I had tried to simulate 433 MHz saw resonator with no em structure(just schematic)in AWR but I could not make it work. Do we need special care to simulate oscillator circuits in AWR? Precharged caps or synthetic noise to initiate oscillation? I will see AWR's examples soon. Finally, does anybody want to demonstrate effect of trace width in a RF circuit(preferably an oscillator) in AWR? Thanks.

AWR or other model based circuit simulators can be used to understand the concepts, but their pre-defined models are made for "classic" microwave line types like microstrip, stripline etc. The situation on chip with conductors embedded in SiO2 with lossy silicon below is not represented by these models. For modelling of on-chip structures, you better use EM based simulation.

For your oscillator question, why don't you create a new thread? It is a much different topic.