Different CMOS transistor width for different output power in a Class E PA

To achieve different output powers at the load of a Class E power amplifier, some papers suggest using a few transistors (NMOS) in parallel with different width. The smaller width, the higher parasitic resistance across the drain and source. This means higher power dissipation and lower efficiency for lower power output option. How should I deal with this issue? The paper I found doesn't discuss this issue. Thanks.