PT中toggle rate的设定顺序
时间:10-02
整理:3721RD
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我在PT里report_power的时候发现设register和clock gating cell的toggle rate顺序调换一下report就会有很大差别。
那么实际上PT设toggle rate的顺序应该是什么呢?
set_switching_activity -toggle_rate 0.05 -clock_domains [all_clocks] -type registers -hierarchy -static_probability 0.5
set_switching_activity -clock_derate 1.0 -clock_domains [all_clocks] -type clock_gating_cells
InternalSwitchingLeakageTotal
Power GroupPowerPowerPowerPower(%)Attrs
--------------------------------------------------------------------------------
clock_network1.11430.07125.361e-041.1860 (54.39%)
register0.25040.02458.116e-040.2756 (12.64%)i
combinational0.22090.37960.01200.6124 (28.09%)
sequential0.00000.00000.00000.0000 ( 0.00%)
memory0.09629.472e-03 7.083e-040.1063 ( 4.88%)
io_pad0.00000.00000.00000.0000 ( 0.00%)
black_box0.00000.00000.00000.0000 ( 0.00%)
Net Switching Power=0.4847(22.23%)
Cell Internal Power=1.6817(77.12%)
Cell Leakage Power=0.0141( 0.65%)
---------
Total Power=2.1805(100.00%)
set_switching_activity -clock_derate 1.0 -clock_domains [all_clocks] -type clock_gating_cells
set_switching_activity -toggle_rate 0.05 -clock_domains [all_clocks] -type registers -hierarchy -static_probability 0.5
InternalSwitchingLeakageTotal
Power GroupPowerPowerPowerPower(%)Attrs
--------------------------------------------------------------------------------
clock_network0.08505.421e-035.361e-040.0909 (10.73%)
register0.04540.02458.137e-040.0707 ( 8.34%)i
combinational0.22060.37900.01200.6116 (72.16%)
sequential0.00000.00000.00000.0000 ( 0.00%)
memory0.0642 9.472e-03 7.083e-040.0743 ( 8.77%)
io_pad0.00000.00000.00000.0000 ( 0.00%)
black_box0.00000.00000.00000.0000 ( 0.00%)
Net Switching Power=0.4184(49.36%)
Cell Internal Power=0.4152(48.98%)
Cell Leakage Power=0.0141( 1.66%)
---------
Total Power=0.8476(100.00%)
那么实际上PT设toggle rate的顺序应该是什么呢?
set_switching_activity -toggle_rate 0.05 -clock_domains [all_clocks] -type registers -hierarchy -static_probability 0.5
set_switching_activity -clock_derate 1.0 -clock_domains [all_clocks] -type clock_gating_cells
InternalSwitchingLeakageTotal
Power GroupPowerPowerPowerPower(%)Attrs
--------------------------------------------------------------------------------
clock_network1.11430.07125.361e-041.1860 (54.39%)
register0.25040.02458.116e-040.2756 (12.64%)i
combinational0.22090.37960.01200.6124 (28.09%)
sequential0.00000.00000.00000.0000 ( 0.00%)
memory0.09629.472e-03 7.083e-040.1063 ( 4.88%)
io_pad0.00000.00000.00000.0000 ( 0.00%)
black_box0.00000.00000.00000.0000 ( 0.00%)
Net Switching Power=0.4847(22.23%)
Cell Internal Power=1.6817(77.12%)
Cell Leakage Power=0.0141( 0.65%)
---------
Total Power=2.1805(100.00%)
set_switching_activity -clock_derate 1.0 -clock_domains [all_clocks] -type clock_gating_cells
set_switching_activity -toggle_rate 0.05 -clock_domains [all_clocks] -type registers -hierarchy -static_probability 0.5
InternalSwitchingLeakageTotal
Power GroupPowerPowerPowerPower(%)Attrs
--------------------------------------------------------------------------------
clock_network0.08505.421e-035.361e-040.0909 (10.73%)
register0.04540.02458.137e-040.0707 ( 8.34%)i
combinational0.22060.37900.01200.6116 (72.16%)
sequential0.00000.00000.00000.0000 ( 0.00%)
memory0.0642 9.472e-03 7.083e-040.0743 ( 8.77%)
io_pad0.00000.00000.00000.0000 ( 0.00%)
black_box0.00000.00000.00000.0000 ( 0.00%)
Net Switching Power=0.4184(49.36%)
Cell Internal Power=0.4152(48.98%)
Cell Leakage Power=0.0141( 1.66%)
---------
Total Power=0.8476(100.00%)
为什么没有人回帖呢,小编的问题解决了吗?能否分享下你的见解