timing violations after ICC route

I read the timing violation report after route in ICC
there are a few lines: I could not understand, please help
-------------report-----------------
clock network delay (propagated)1.051.05
I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/CP (dfcrq4)
0.001.05 r
I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/Q (dfcrq4)12.86 @13.91 f
I_ORCA_TOP/I_PCI_CORE/pframe_n_out (PCI_CORE_pci_data_width16)
0.0013.91
--------------------------------------
Q1: where is 12.86, above in red, coming from?
Q2: a simple DFF, dfcrq4 in this case, clock 2 Q would never be 12.86ns, I did check the wire connect to Q
only 120u at the most, and CP wire is only 500u at most
Q3: sdc did not define pin loading though, could that be the reason?
Please help

need an expert for those questions

可以开report_timing -verbose 看一下transition value是不是正常，正常情况下tool不该查出这么大的clk2q delay

可以查看下这个cell的fanout。

all_connect看连接了多少个cell

Thank you kevin_zlm, for the reply
I don't know how to find out the fanout of the cell instance:
I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_
but from the layout I could tell it is only one-to-one to the pin, pframe_n, the wire is only about 120u
and the cell, dfcrq4, should be good enough

thank you, hjacky2010, for replying
how do we check the transition time, report_timing -verbose did not work,

fanout and transition time ：report_timing -to * -derate -transition_time

Thank you, kevin_zlm, that worked:
PointFanoutTransDerateIncrPath
----------------------------------------------------------------------------------------------
clock PCI_CLK (rise edge)0.000.00
clock network delay (propagated)1.051.05
I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/CP (dfcrq4)
0.290.001.05 r
I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/Q (dfcrq4)30.6812.86 @13.91 f
I_ORCA_TOP/I_PCI_CORE/pframe_n_out (net)10.0013.91 f
I_ORCA_TOP/I_PCI_CORE/pframe_n_out (PCI_CORE_pci_data_width16)0.0013.91 f
-------------------------------------------------------------------------------------------------
but why trans reported 30.68, where did it come from?

report_delay_calculation

thanks

report_timing -cap -net -trans

Thank you, kevin_zlm, for your replyIt is quite a surprise, ICC placement and route procedures should see the same information, Why didn't placement or route insert a buffer between Q and pin pframe_n to avoid DFF Q directly drive that 15pF?
Please help

report_delay_calculation -fromI_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/CP -to I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/Q
report:
---------------------------
Arnoldi-based Delay Calculation:
RC network on pin 'I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/Q' :
------------------------------------------------------
Number of elements = 8 Capacitances + 7 Resistances
Total capacitance= 15.014811 pF
Total capacitance= 15.014811 (in main library unit)
Total resistance= 0.078812 Kohm
RiseFall
------------------------------------------------------------------
Input transition time= 0.2868310.293038(in main library unit)
Effective capacitance= 13.72946414.193019(in pF)
Effective capacitance= 13.72946414.193019(in main library unit)
Drive resistance= 0.6506810.647745(in Kohm)
Output transition time = 26.55496830.681604(in main library unit)
Cell delay= 9.91471512.855111(in main library unit)