calibre中怎么用v2lvs把verilog网表转换成spice网表

v2lvs -v verilog_design_file -o output_spice_file
[-l verilog_lib_file] [-lsp spice_library_file]
[-lsr spice_library_file] [-s spice_library_file]
[-s0 groundnet] [-s1 powernet] [-sk]
[-p prefix] [-w warning_level]
[-a array_delimiters] [-c char1[char2]]
[-u unnamed_pin_prefix] [-t svdb_dir] [-addpin pin_name]
[-b] [-n] [-i] [-e] [-h]
[-cb][-ictrace]
Arguments
· -v verilog_design_file
Specifies the filename of the input Verilog structural netlist.
· -o output_spice_file
Specifies where to place the output LVS SPICE netlist. Default is standard out.
· -l verilog_lib_file
Specifies the location of the Verilog primitive library file. It is not translated.
· -lsp spice_library_file
Specifies SPICE library file name using pin mode. The SPICE file is parsed for
interface configurations. Pins with pin select ([ ]) annotation are kept as
individual pins using escaped identifiers.
· -lsr spice_library_file
Specifies SPICE library file name using range mode. The SPICE file is parsed
for interface configurations. Pins with pin select ([ ]) annotation are assembled
into Verilog ranges.
· -s spice_library_file
Specifies that the -o output file have a .INCLUDE statement placed at the
beginning that points to the SPICE library file.
· -s0 groundnet
Specifies the default net name for mapping to pin connections with a value of
zero (0). Outputs the specified names in place of Verilog supply0 nets and
generates .GLOBAL declarations in the output netlist.
· -s1 powernet
Specifies the default net name for mapping to pin connections with a value of
one (1). Outputs the specified names in place of Verilog supply1 nets and
generates .GLOBAL declarations in the output netlist.
· -sk
Specifies that Verilog supply0 and supply1 nets are not connected to the global
power and ground nets.
· -p prefix
Adds prefix to Verilog gate level primitive cells.
· -w warning_level
Controls the amount of warning message output. Possible level choices are:
0 Selects to output no warning messages.
1 Selects to output warning messages for skipped blocks and modules only.
2 Selects to output level 1 and calls to undeclared modules and pin arrays
with widths wider than ports. This is the default.
3 Selects to output level 2 and called port array mismatches and
unsupported compiler directives.
4 Selects output level 3 plus all ignored constructs.
· -a array_delimiters
Changes the array delimiter characters. The default is [ ].
· -c char1[char2]
Sets the substitution characters for escaped identifier characters illegal in
SPICE. char1 replaces $, comma, (, ), and =. char2 replaces /. No space is
needed between the two user-supplied arguments.
· -u unnamed_pin_prefix
Specifies a prefix to add to unnamed pin connections in module instantiations.
· -t svdb_dir
Adds source netlist pin direction information to the SVDB. This is used in
Calibre xRC.
· -addpin pin_name

问前可先google一下

同意楼上

这里的verilog网表指你APR后的网表。

不错...

有用的东西收下，多谢回答

不错啊

verilog网表指你APR后的网表

v2lvs -v verilog -o x.cdl

包含的具体的单元的网表或者SRAM的网表，你可以在生成的cdl中INCLUDE进去

如果仅仅是门级的，去掉几个括号，加上电源地好像就可以了

学到了！

还要把标准单元库的cdl也加进去

请问楼上的标准单元库怎么加?

学习了，谢谢！

呵呵，不错了

不錯，好東東

学习了~

就是v2lvs，hercules有个组件叫做 nettran
都是一样的东西

to icfbicfb:
Yes Hercles Net and Calibre V2LVS are equivalent.

.v档都是APR之后吗?

是这样子的~

关键就这句：v2lvs -v verilog_design_file -o output_spice_file
不会看calibre 手册，是用的calibre工具来的

xue xi

主要就是用
v2lvs -v-o -s0 -s1-s
-l 很少用， 不是必要的，

学习了，谢谢

2L经典

请问可以将cdl转换成.v网表吗?

生成的网表子电路端口和标准单元转换的子电路端口如何匹配 不可能手工匹配吧 VDD VSS 是一目了然 其它端口呢?

我想问APR 是什么?