Calibre做lvs出现的问题，求助！
时间：10-02
整理：3721RD
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CELL COMPARISON RESULTS ( TOP LEVEL )
##########################
# ###
##NOT COMPARED#
# ###
##########################
Error:Different numbers of ports (see below).
Error:Power net missing in layout. Ground net missing in layout.
LAYOUT CELL NAME:fsm_3always
SOURCE CELL NAME:fsm_3always
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
LayoutSourceComponent Type
--------------------------
Ports:011*
Nets:162163*
Instances:337325*MN (4 pins)
338324*MP (4 pins)
------------
Total Inst:675649
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
LayoutSourceComponent Type
--------------------------
Ports:010*
Nets:8585
Instances:118*MN (4 pins)
96*MP (4 pins)
03*INV (2 pins)
01*SPDW_2_1_1 (5 pins)
02*SPDW_2_2 (5 pins)
02*SPUP_2_1 (4 pins)
02*SPUP_2_2_1 (6 pins)
10*SPMN_2_1_1 (6 pins)
20*SPMN_2_2 (6 pins)
20*SPMP_2_1 (5 pins)
20*SPMP_2_2_1 (7 pins)
33_invb (6 pins)
3838_invv (4 pins)
88_invx2v (4 pins)
11_invx4v (4 pins)
33_nand2v (5 pins)
11_nand3v (6 pins)
33_nand4v (7 pins)
22_nor2v (5 pins)
11_nor4v (7 pins)
2020_sdw2v (4 pins)
1717_smp2v (4 pins)
------------
Total Inst:124121
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
o Statistics:
1 passthrough source net was deleted.
453 layout mos transistors were reduced to 80.
373 mos transistors were deleted by parallel reduction.
414 source mos transistors were reduced to 67.
347 mos transistors were deleted by parallel reduction.
##########################
# ###
##NOT COMPARED#
# ###
##########################
Error:Different numbers of ports (see below).
Error:Power net missing in layout. Ground net missing in layout.
LAYOUT CELL NAME:fsm_3always
SOURCE CELL NAME:fsm_3always
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
LayoutSourceComponent Type
--------------------------
Ports:011*
Nets:162163*
Instances:337325*MN (4 pins)
338324*MP (4 pins)
------------
Total Inst:675649
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
LayoutSourceComponent Type
--------------------------
Ports:010*
Nets:8585
Instances:118*MN (4 pins)
96*MP (4 pins)
03*INV (2 pins)
01*SPDW_2_1_1 (5 pins)
02*SPDW_2_2 (5 pins)
02*SPUP_2_1 (4 pins)
02*SPUP_2_2_1 (6 pins)
10*SPMN_2_1_1 (6 pins)
20*SPMN_2_2 (6 pins)
20*SPMP_2_1 (5 pins)
20*SPMP_2_2_1 (7 pins)
33_invb (6 pins)
3838_invv (4 pins)
88_invx2v (4 pins)
11_invx4v (4 pins)
33_nand2v (5 pins)
11_nand3v (6 pins)
33_nand4v (7 pins)
22_nor2v (5 pins)
11_nor4v (7 pins)
2020_sdw2v (4 pins)
1717_smp2v (4 pins)
------------
Total Inst:124121
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
o Statistics:
1 passthrough source net was deleted.
453 layout mos transistors were reduced to 80.
373 mos transistors were deleted by parallel reduction.
414 source mos transistors were reduced to 67.
347 mos transistors were deleted by parallel reduction.
请教各位大神，怎么我的layout里一个port也没有
没打label造成的?我也不是很清楚
楼上正解，就是没有label造成的
打了label，是用pin那层金属打的
打terminal就可以，打text也可以，我想问你，你如果在ICC中去debug，是怎么定位到哪个port有问题的?我在report中并没有看到提示是哪个port出问题
port为0，一定是你label没打好--- 仔细研读下DR吧
查下你的lvs rule 是不是 text map 的层次错了，看下gds里的text是不是和 rule里层次一致
用text那层打
请问，如果在ICC中去debug，是怎么定位到哪个port有问题的?我在report中并没有看到提示是哪个port出问题
lable层次不对吧?