关于bottom-up下的critical path问题

请教各位前辈！我最近在用bottom-up的方式做综合，具体的流程与下面这段code一样，但是在timing上碰到了问题。我在synthesize 所有subblock的时候，DC给出的最长的路径不超过4ns，但是在做top-level synthesize的时候，最长的路径却变成了10ns，我对所有的subblock都做了set_dont_touch,但是貌似没有用。我参考的code如下：

remove_design –all

read_verilog DoubleCore.v

current_design AddressGenerator

Link

check_design

include subblocks.const

compile -map_effort high

report_timing -path full -delaymax -max_paths 20 -nworst 100

#Generate Verilog Netlist and ddcand sdf

write -hierarchy -format verilog-output"/home/AddressGenerator.v“

write -hierarchy -format ddc-output"/home/AddressGenerator.ddc“

write_sdf"/home/AddressGenerator.sdf“

report_power

current_design fixmultiply

Link

check_design

include subblocks.const

compile -map_effort high

report_timing -path full -delaymax -max_paths 20 -nworst 100

#Generate Verilog Netlist and ddcand sdf

write -hierarchy -format verilog-output "/home/fixmultiply.v“

write -hierarchy -format ddc-output "/home/fixmultiply.ddc“

write_sdf"/home/fixmultiply.sdf“

report_power

current_design expon

Link

check_design

include subblocks.const

compile -map_effort high

report_timing -path full -delaymax -max_paths 20 -nworst 100

#Generate Verilog Netlist and ddcand sdf

write -hierarchy -format verilog-output "/home/expon.v“

write -hierarchy -format ddc-output "/home/expon.ddc“

write_sdf "/home/expon.sdf“

report_power

current_design MMU

Link

check_design

include subblocks.const

compile -map_effort high

report_timing -path full -delaymax -max_paths 20 -nworst 100

#Generate Verilog Netlist and ddcand sdf

write -hierarchy -format verilog-output "/home/MMU.v“

write -hierarchy -format ddc-output "/home/MMU.ddc“

write_sdf "/home/MMU.sdf“

report_power

current_design FSM

Link

check_design

include subblocks.const

compile -map_effort high

report_timing -path full -delaymax -max_paths 20 -nworst 100

#Generate Verilog Netlist and ddcand sdf

write -hierarchy -format verilog-output "/home/FSM.v“

write -hierarchy -format ddc-output "/home/FSM.ddc“

write_sdf "/home/FSM.sdf“

report_power

current_design MUX_A

Link

check_design

include subblocks.const

compile -map_effort high

report_timing -path full -delaymax -max_paths 20 -nworst 100

#Generate Verilog Netlist and ddcand sdf

write -hierarchy -format verilog-output "/home/ MUX_A.v“

write -hierarchy -format ddc-output "/home/ MUX_A.ddc“

write_sdf "/home/ MUX_A.sdf“

report_power

current_design MUX_D

Link

check_design

include subblocks.const

compile -map_effort high

report_timing -path full -delaymax -max_paths 20 -nworst 100

#Generate Verilog Netlist and ddcand sdf

write -hierarchy -format verilog-output "/home/ MUX_D.v“

write -hierarchy -format ddc-output "/home/ MUX_D.ddc“

write_sdf "/home/ MUX_D.sdf“

report_power

current_design GlobalFSM

Link

check_design

include subblocks.const

compile -map_effort high

report_timing -path full -delaymax -max_paths 20 -nworst 100

#Generate Verilog Netlist and ddcand sdf

write -hierarchy -format verilog-output "/home/ GlobalFSM.v“

write -hierarchy -format ddc-output "/home/ GlobalFSM.ddc“

write_sdf "/home/GlobalFSM.sdf“

report_power

current_design LayerTrans

Link

check_design

include subblocks.const

compile -map_effort high

report_timing -path full -delaymax -max_paths 20 -nworst 100

#Generate Verilog Netlist and ddcand sdf

write -hierarchy -format verilog-output "/home/ LayerTrans.v“

write -hierarchy -format ddc-output "/home/ LayerTrans.ddc“

write_sdf "/home/LayerTrans.sdf“

report_power

current_design Core

Link

check_design

include subblocks.const

compile -map_effort high

report_timing -path full -delaymax -max_paths 20 -nworst 100

#Generate Verilog Netlist and ddcand sdf

write -hierarchy -format verilog-output "/home/ Core.v“

write -hierarchy -format ddc-output "/home/Core.ddc“

write_sdf "/home/LearningUnit.sdf“

report_power

remove_design –all

read_ddc [list"/home/LearningUnit.ddc"]

read_ddc [list"/home/MMU.ddc"]

read_ddc [list"/home/FSM.ddc"]

read_ddc [list"/home/MUX_A.ddc"]

read_ddc [list"/home/MUX_D.ddc"]

read_ddc [list"/home/GlobalFSM.ddc"]

read_ddc [list"/home/LayerTrans.ddc"]

read_verilog [list"/home/TOP.v"]

current_design TOP

set_dont_touch Learning

set_dont_touch MMU

set_dont_touch FSM

set_dont_touch MUX_A

set_dont_touch MUX_D

set_dont_touch GlobalFSM

set_dont_touch LayerTrans

check_design

include top.const

compile -map_effort high

report_timing -path full -delaymax -max_paths 20 -nworst 100

write_sdc "/home/TOP.sdc“

write -hierarchy -format verilog-output"/home/TOP_nl.v“

write_sdf"/home/TOP.sdf"report_power

来自 <http://bbs.eetop.cn/thread-404761-1-1.html>

希望各位大神指点一下！

猜测，是因为顶层考虑了各个子模块的互连问题导致的，这个时候他是会在连线上插buf之类的。

谢谢你的回复！我又检查了一下top level的综合结果，发现最长的路径是在两个subblock之间，我怀疑是因为其中一个subblock的input没有加register，所以在做subblock单独综合的时候，timing constrain没有约束到该subblock input的combination logic。我现在想可以把那两个subblock合并成一个大的subblock来综合。