为什么Encounter CTS之后报的phase delay和latency值不同

用EDI做完tree之后，ckSynthesis -report reports/cts/clock.rpt里面看到的phase delay如下：
###############################################################
# Complete Clock Tree Timing Report
#
# CLOCK: clk
#
# Mode: clkRouteOnly
#
# Delay Corner information
# Analysis View: wc_cworst_func
# Delay Corner Name: dc_wc
# RC Corner Name: cworst_125c
# Analysis View: wcl_cworst_func
# Delay Corner Name: dc_wcl
# RC Corner Name: cworst_m40c
# Analysis View: lt_cbest_func
# Delay Corner Name: dc_cblt
# RC Corner Name: cbest_m40c
# Analysis View: lt_cbest_scan
# Delay Corner Name: dc_cblt
# RC Corner Name: cbest_m40c
###############################################################

Nr. of Subtrees: 225
Nr. of Sinks: 9493
Nr. of Buffer: 975
Nr. of Level (including gates) : 25
Root Rise Input Tran: 0.1(ps)
Root Fall Input Tran: 0.1(ps)
No Driving Cell Specified！
Max trig. edge delay at sink(R): ****/dout_1d_reg_28_/CK 2924.6(ps)
Min trig. edge delay at sink(R): ****/availCnt_reg_6_/CK 2777.5(ps)
(Actual)(Required)
Rise Phase Delay: 2777.5~2924.6(ps)0~10(ps)
Fall Phase Delay: 2798.2~3082.2(ps)0~10(ps)
Trig. Edge Skew: 147.1(ps)150.3(ps)
Rise Skew: 147.1(ps)

但是，运行report_clock_timing -type skew得到的结果却是：
Clock: clk
Analysis View: wc_cworst_func
SkewLatencyCPPRClock Pin
---------------------------------------------------------------------------
2.103r****/arrFiFo_reg_41__1_/CK
0.2261.832-0.044r****/availCnt_reg_0_/CK

为何两边报的insertion delay和skew都差别这么大?

phase delay可能有derate值吧， 一般看phase delay，

report_clock_timing -type skew 的skew是wc_cworst_func corner下的值，但clock.rpt中的skew是哪个corner的呢? corner不同skew自然也不会相同。

刚刚确认了一下，latency 确实不含OCV因素，那应该就是小编说的原因了，谢谢

update I/O latency
你的clock root上可能有source latency

学习了为什么我发的帖子没人回答