CTS 优化不下去.
Beginning Phase 1 Design Rule Fixing(m
ax_transition)(max_fanout)(max_capacitance)
------------------------------------
ELAPSEDWORST NEG TOTAL NEGDESIGNMIN DELAY
TIMEAREASLACKSLACKRULE COSTENDPOINTCOST
--------- --------- --------- --------- --------- ------------------------- ---------
0:00:1921571.33.9139.1210.70.00
0:00:3122160.93.9139.1206.8 top/sub1/sub2/..._reg[12]/D -11384.68
0:00:4523202.23.9139.1206.8 top/sub1/sub2/..._reg[13]/D -10736.12
后面的负值减小的过程中,芯片的利用率已经到１００%了,fail.
请问是什么原因,后面的min delay cost是说的hold violation吗?
为什么会有这么大的负值?约束不合理,还是?
先行谢过各位了！
面积用光了，放不下东西了。
thanks hawkz, could you give me some detailed info:
1.the utilization after placement is 60%, the 40% left is not enough for CTS optimizations?
2.and negative slack is hold violations or ?
regards.
按照你Placement的时候Utilization是60%，到了ＣＴＳ变成１００％是显然不正常的，普通设计增加个5%就了不得了，所以建议你还是仔细研究下你的Clock结构和CTS spec file的用法，肯定是有错的地方。
另外你也要查查你做timing optimization有没有问题，先不用管violation了，你都没面积了，有violation也没办法，不过到最后Hold violation是不能有的。
thanks again. and I would be most appreciate if your could offer some additional help:
(1), could you please explain the negative slack presented in the log files of ICC
(2), could you offer some suggestions on where to check:
a, SDC file is not properly defined? for hold checks on the input and output, I left 20% clock cycle for input/output delay.
b, CTS target is not right?
or any other possible reasons?
regards.
不好意思我不熟ICC，还是等坛子里其他ICC高手来解释。不过我想说的是你这个结果很不正常，所以不必拘泥于工具的报告，而应该检查一下你的Netlist和sdc，看你的时钟定义是不是对?有没有遗漏?
像你log里面的Slack多半是因为sdc的设置错误造成的，正所谓garbage in，garbage out不是吗?
Thanks again.
min delay 是hold timing，有可能是fix hold造成的饿，
请不要一步做clock_opt因为他包括cts和opt，
一般是clock_opt -only_cts
set_fix_hold [all_clocks]
psynopt
thanks icfb,
that's what I did, and the report is generated during clock optimization.
so , please divide clock & opt to seperated steps ,
first make sure before opt the utilization is reasonable , save as a backup cell ,
面积不够吧
尝试着做一下网表优化,再看看你的FP 是否合理啊?
2种可能。
1. SDC有问题。
2. Clock Tree是否有问题。
建议先在Opt之前，先报下Timing， Setup 和HOLD。
个人建议是好好关注下HOLD。
icc里能修到100%啊
thanks all.
and I check the hold violations, and found one strange things:
the clock network delay is always much bigger in Required path than in Arrival path.to put it simply:
(1), I set the network delay(network + source = 2ns) in SDC before CTS, but the value of the clock network delay(ideal) is ranged from 5 to 10(before CTS), and the value in RT is much bigger than AT, why?
(2), after CTS the propagated network delay(propagated): values in RT is also much bigger than AT, why ?
thanks in advance.
很有可能是你的uncertainty clock 加在了hold 上面了，而且加的很大吧。
小编，我做CTS时也遇到类似的问题，placement做完后利用率才65%，但fix hold time后就100%了，我建时钟树和修hold time是分开做的。
查看报告发现，建时钟树时遇到了error：
initializing parameters for clock ate_clk:
root pin: pin/clk_buf_scan/clk_buf/Z
Error: skipping pin pin/clk_buf_scan/clk_buf/Z because it's not on clock network.(CTS-555)
CTS-555的意思是该pin不在clock network上，或者在该pin的fanout路径中的某点被定义了set_case_analysis或者set_disable_timing，
请问这个问题怎么解啊，和前端designer一起debug 1周多了，没找出根源，求小编赐教。
小编，我在cts时也遇到了类似的问题，placement做完后利用率只有65%，但fix hold time后利用率100%了，我建时钟树和fix hold time是分开两步做的。
查看报告，发现在建时钟树时报了一个error：
initializing parameters for clock ate_clk:
root pin:pin/clk_buf_scan/clk_buf/Z
Error:skipping pin pin/clk_buf_scan/clk_buf/Z because it's not on clock network.(CTS-555)
CTS-555的意思是该pin不在clock network上，或者在该pin的fanout上的某点被set_case_analysis或set_disable_timing了。
请问这个问题怎么解啊，和前端designer一起debug 1周多了，没找出根源，求小编指教！