IO PAD的P/G connection问题

大家好我的输入输出IO PAD是在RTL时例化加上的，逻辑综合以后，在脚本里面加电源PAD
分别加在芯片四周
#3.3V
create_cell {VSSHL VSSHR VSSHT VSSHB} PL_DUP_01_VSSH
create_cell {VDDHL VDDHR VDDHT VDDHB} PL_DUP_01_VDDH
#1.8V
create_cell {VSSLL VSSLR VSSLT VSSLB} PL_DUP_01_VSSC
create_cell {VDDLL VDDLR VDDLT VDDLB} PL_DUP_01_VDDC

按网上的说法是，3.3V是给IO 供电的，1.8V是给core供电的。我PNS时supply是1.62V
然后在floorplan里面
insert_pad_filler
(filler添加的没有问题，但是没明白为什么加了filler就生成了power ring，以及和下面的create_pad_ring的关系
datasheet里面说fill the gaps between the pads to connect all the power rings, the ground rings and the guard rings)
derive_pg_connection \

-power_net VDD -power_pin VDD \
-ground_net GND -ground_pin GND

derive_pg_connection \

-power_net VDDH -power_pin VDDH \
-ground_net VSSH -ground_pin VSSH
derive_pg_connection \

-power_net VDD\
-ground_net GND\
-tie

derive_pg_connection -reconnect
最后的报告是
Power/Ground Connection Summary:
P/G net nameP/G pin count(previous/current)
--------------------------------------------------------------------
Other power nets:14092/14092
Unconnected power pins:1/1
Other ground nets:14092/14092
Unconnected ground pins:0/0
--------------------------------------------------------------------
Warning: Power connection/checking is skipped for 28185 power pins because the required power pin information cannot be found in logical libraries. (MV-510)
1
提示有一个power pin没连接，怎么找到这个没连接的power pin呢
create_pad_rings
整个电源IO就是按上面这些步骤做的
这时候看pad里面VDD GND VDDH VSSH pin的属性，net都是连接上的
但是最后
verify_pg_connection的时候，报告
Checking [VDDH]:
There are no floating shapes
ERROR: There are 58 floating pins
Checking [GND]:
There are no floating shapes
ERROR: There are 60 floating pins
Checking [VDD]:
There are no floating shapes
ERROR: There are 57 floating pins
Checking [VSSH]:
There are no floating shapes
ERROR: There are 58 floating pins
Checked 4 nets, 4 have Errors

用error browser看，高亮的错误都是IO pad上这四个pin
请问下这是什么情况呢
PNS参数
synthesize_fp_rail \
-nets {VDD GND} \
-voltage_supply 1.62 \
-target_voltage_drop 200 \
-synthesize_power_plan \
-pad_masters {PL_DUP_01_VSSC PL_DUP_01_VDDC} \
-analyze_power
commit_fp_rail

我的整个电源IO命令和约束就这些了，应该都讲清楚了吧，求解...

顶一下

insert_pad_filler以后，就不需要create_pad_ring了， 这个命令几乎太老，用不到，
至于padring上的pg verify，可以忽略，加了filler，自动会abut在一起的，到后面calibre才能看出来，
icc看不清楚的

正好解决了我的疑惑，谢谢

顶一下~

学习了