cannot find the design ‘DW02_mult_3_stage’ in the WROK
求大神们顶起来啊这个问题困扰我了好几天 求解答啊跪求啊
这是designware吧，不知道你有没有设置下面的库
set_app_var synthetic_library dc/libraries/syn/dw_foundation.sldb
单纯设置一个search_path应该是没用的
仍然报warning啊，求大神指教，我在我隐藏文件设置了您给的命令，还是不好使啊。
路径按照你的DC安装路径修改了吗?确认下dc启动时dw_foundation.sldb是否载入了
我在隐藏文件下设置了，又在dc_shell命令行下也设置了，虽然没显示1 但是感觉是读进去了。在后面的log中也load它了，不过还是报那个warnning。 不知道是为何啊。
Presto compilation completed successfully.
Loading db file '/home/soc_test/ss/libraries/syn/dw_foundation.sldb'
Elaborated 1 design.
Current design is now 'Mon'.
Information: Building the design 'dsp_0000'. (HDL-193）
这是其中的log, 这应该是表名读进去dw_foundation.sldb了吧。
但是后面还报
Presto compilation completed successfully.
Information: Building the design 'DW02_mult_3_stage' instantiated from design 'dsp_0000' with
the parameters "16,16". (HDL-193)
Warning: Cannot find the design 'DW02_mult_3_stage' in the library 'WORK'. (LBR-1)
Warning: Design 'Mon' has '4' unresolved references. For more detailed information, use the "link" command. (UID-341)
Current design is 'Mon'.
这是为何啊，求指教啊
库里面没有DW02_mult_3_stage吧
有的我用report_design_lib如下显示
dc_shell> report_design_lib
****************************************
Report : hdl libraries
Version: J-2014.09-SP1
Date: Fri Jul 24 17:14:33 2015
****************************************
Contents of current design libraries
CCSC (/home/soc_test/ss/packages/ccsc/lib)
This library does not contain any valid design units.
CD (/home/soc_test/ss/packages/CD/lib)
Error: The library 'CD' is mapped to the directory '/home/soc_test/ss/packages/CD/lib', which is not readable. (LBR-2)
COMDISCO_MVL9 (/home/soc_test/ss/packages/comdisco/lib)
Error: The library 'COMDISCO_MVL9' is mapped to the directory '/home/soc_test/ss/packages/comdisco/lib', which is not readable. (LBR-2)
DEFAULT (/home/soc_test/desktop/dc/work)
WORK (/home/soc_test/desktop/dc/work)
architecture:mMon(verilog)
architecture:mdsp_0000(verilog)
architecture:mdsp_0001(verilog)
architecture:mdsp_fffe(verilog)
architecture:mdsp_ffff(verilog)
DW01 (/home/soc_test/ss/dw/dw01/lib)
后面还有DW02 DW03等等很多我就不全复制了。 我有个疑问 为什么我的WORK里只有那四个我读入的网表 而DW02是自己单独的一个库呢。求大神指导啊。
我刚看了下，可能是大小写的问题，应该是写为“DW02_MULT_3_STAGE”
大侠，我将RTL里面的小写改成了大写，还是报warning
Presto compilation completed successfully.
Information: Building the design 'DW02_MULT_3_STAGE' instantiated from design 'dsp_0000' with
the parameters "16,16". (HDL-193)
Warning: Cannot find the design 'DW02_MULT_3_STAGE' in the library 'WORK'. (LBR-1)
Warning: Design 'Mon' has '4' unresolved references. For more detailed information, use the "link" command. (UID-341)
Current design is 'Mon'.
我发现个问题， 就是它只在 library 'WORK'里找DW02_MULT_3_STAGE，但是我用report_desgin_lib中，
DEFAULT (/home/soc_test/desktop/dc/work)
WORK (/home/soc_test/desktop/dc/work)
architecture:mMon(verilog)
architecture:mdsp_0000(verilog)
architecture:mdsp_0001(verilog)
architecture:mdsp_fffe(verilog)
architecture:mdsp_ffff(verilog)
DW01 (/home/soc_test/ss/dw/dw01/lib)
DW02 (/home/soc_test/ss/dw/dw01/lib)
entity: p nDW02_BOOTH
architecture:mn dDW02_BOOTH(STR)
package:nDW02_COMPONENTS
entity: p nDW02_MAC
architecture:mnDW02_MAC(VERIF)
entity: p nDW02_MULT
architecture:mn dDW02_MULT(CSA)
architecture:nDW02_MULT(VERIF)
entity: p nDW02_MULTP
architecture:n dDW02_MULTP(NBW)
architecture:mn dDW02_MULTP(WALL)
entity: p nDW02_MULT_2_STAGE
architecture:mn dDW02_MULT_2_STAGE(STR)
entity: p nDW02_MULT_3_STAGE
architecture:mn dDW02_MULT_3_STAGE(STR)
entity: p nDW02_MULT_4_STAGE
architecture:mn dDW02_MULT_4_STAGE(STR)
从上面报告中可以看出，DW02_MULT_3_STAGE是在DW02中，而不在WORK中，所以会报那个warning，但是不知道怎么解决啊。
已经解决啦谢谢大侠帮助哈。