about reset pin timing check

my reset signal is come from clk port after some logic cell , so in encouter , it will ckeck reset pin's timing with clk fall edge ,
thus setup violation is larger due it introduced half cycle at data path , so how to deal with it in SDC contrains file ?
it means reset singal and clock signal is from the same root ,

input delay可以设小点，或者干脆false path，