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uvm phase

时间:10-02 整理:3721RD 点击:
class driver_2 extends uvm_driver#(cmd);
`uvm_component_utils(driver_2)
virtual cmd_if vif;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
void'(uvm_config_db#(virtual cmd_if)::get(this, "", "vif", vif));
endfunction
task run_phase(uvm_phase phase);
vif.cmd_en<= 1'b0;
vif.op<= 1'b0;
vif.addr<= 8'b0;
vif.wr_data <= 8'b0;
while(!vif.rst_n)
@(posedge vif.clk);
while(1) begin
seq_item_port.get_next_item(req);
//begin_tr(req);
@(posedge vif.clk);
vif.cmd_en<= 1'b1;
vif.wr_data <= ((req.op == R) ? 0 : req.wr_data);
vif.addr<= req.addr;
vif.op<= ((req.op == R) ? 0 : 1);
@(posedge vif.clk);
vif.cmd_en<= 1'b0;
vif.wr_data <= 8'b0;
vif.addr<= 8'b0;
vif.op<= 1'b0;
//end_tr(req);
@(posedge vif.clk);
if(req.op == R) begin //注意这里!
req.rd_data = vif.rd_data;
end
seq_item_port.item_done();
end
endtask
在代码里build phase和run phase的作用是什么,为什么要用它们?各位大神帮帮忙

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