EDI关于clock gating的timing检查，PhaseShift=0？

SD_CLK周期为10ns，下面是一条rise launtch到fall capture的path，为何phase shift 为0?
Path 16: VIOLATED Clock Gating Setup Check with Pin dig_top_inst/sd_ctrl_top/U_DWC_mobile_storage_ciu/U_DWC_mobile_storage_muxdemux/clk_gate_cdata_in_sample_2_reg/latch/CKN

Endpoint: dig_top_inst/sd_ctrl_top/U_DWC_mobile_storage_ciu/U_DWC_mobile_storage_muxdemux/clk_gate_cdata_in_sample_2_reg/latch/E (v) checked with trailing edge of 'SD_CLK'
Beginpoint: dig_top_inst/sd_ctrl_top/U_DWC_mobile_storage_ciu/U_DWC_mobile_storage_cmdpath/cp_card_num_reg_0_/Q (^) triggered by leading edge of 'SD_CLK'
Path Groups:{reg2reg} {clkgate}
Other End Arrival Time10.13
- Clock Gating Setup0.34
+ Phase Shift0.00
+ CPPR Adjustment0.06
- Uncertainty0.30
= Required Time9.54
- Arrival Time12.15
= Slack Time-2.61
Clock Rise Edge0.00
= Beginpoint Arrival Time0.00
Timing Path:
+------------------------------------------------------------------------------------------------------------------+
|Instance|Cell|Arc| Delay | Arrival |Slew |Load |
|||||Time|||
|----------------------------------------------------+-------------+-------------+-------+---------+-------+-------|
| dig_top_inst/apb1_inst/sys_config_inst/syspll_clk_ || Z ^||0.00 |0.00 |0.02 |
| main_clkbuf/donttouch_clk_buf4|||||||

| dig_top_inst/apb1_inst/sys_config_inst/intb1_clkdi | OR2HD4X| B ^ -> Z ^|0.16 |2.69 |0.08 |0.02 |
| v_ssp0clk/z_int_clk_cg/donttouch_or2|||||||

| dig_top_inst/sd_ctrl_top/U_DWC_mobile_storage_ciu/ | FFSDRHD4X| CK ^ -> Q ^ |0.56 |9.83 |0.18 |0.06 |
| U_DWC_mobile_storage_cmdpath/cp_card_num_reg_0_|||||||

| dig_top_inst/sd_ctrl_top/U_DWC_mobile_storage_ciu/ | CLKGTNPHD4X | E v|0.01 |12.15 |0.20 |0.08 |
| U_DWC_mobile_storage_muxdemux/clk_gate_cdata_in_sa |||||||
| mple_2_reg/latch|||||||
+------------------------------------------------------------------------------------------------------------------+
Clock Rise Edge0.00
= Beginpoint Arrival Time0.00
Other End Path:
+------------------------------------------------------------------------------------------------------------------+
|Instance|Cell|Arc| Delay | Arrival |Slew |Load |
|||||Time|||
|----------------------------------------------------+-------------+-------------+-------+---------+-------+-------|
| dig_top_inst/apb1_inst/sys_config_inst/syspll_clk_ || Z ^||0.00 |0.00 |0.02 |
| main_clkbuf/donttouch_clk_buf4|||||||
| dig_top_inst/apb1_inst/sys_config_inst/syspll_clk_ | BUFCLKHD4X| A ^ -> Z ^|0.12 |0.12 |0.05 |0.00 |
| main_Exclude_0|||||||
| dig_top_inst/apb1_inst/sys_config_inst/clk_switch_ | CLKGTPHD4X| CK ^ -> Z ^ |0.39 |0.51 |0.09 |0.01 |
| mainclk/clkgate_inst_clk1/donttouch_icg_inst|||||||
| dig_top_inst/apb1_inst/sys_config_inst/clk_switch_ | OR4HD4X| B ^ -> Z ^|0.41 |0.93 |0.37 |0.15 |
| mainclk/or4_inst/donttouch_or4|||||||
| dig_top_inst/apb1_inst/sys_config_inst/clkmux_inst | MUX2HD4X| B ^ -> Z ^|0.30 |1.22 |0.12 |0.03 |
| _ssp0clk_ref/donttouch_clkmux2|||||||
| dig_top_inst/apb1_inst/sys_config_inst/ssp0_pclk_r | INVCLKHD8X| A ^ -> Z v|0.16 |1.38 |0.20 |0.16 |
| ef_raw_L1_I0|||||||
| dig_top_inst/apb1_inst/sys_config_inst/ssp0_pclk_r | INVCLKHD20X | A v -> Z ^|0.06 |1.44 |0.05 |0.00 |
| ef_raw_L2_I1|||||||
| dig_top_inst/apb1_inst/sys_config_inst/clkgate_ins | CLKGTPHD12X | CK ^ -> Z ^ |0.41 |1.85 |0.11 |0.07 |
| t_ssp0clk/donttouch_icg_inst|||||||
| dig_top_inst/apb1_inst/sys_config_inst/intb1_clkdi | FFSDHD4X| CK ^ -> Q v |0.42 |2.27 |0.07 |0.02 |
| v_ssp0clk/int_clk_posedge_xor_reg|||||||
| dig_top_inst/apb1_inst/sys_config_inst/intb1_clkdi | MUX2HD4X| S0 v -> Z v |0.23 |2.50 |0.09 |0.01 |
| v_ssp0clk/z_int_clk_pre_xor_cg/donttouch_clkmux2|||||||
| dig_top_inst/apb1_inst/sys_config_inst/intb1_clkdi | OR2HD4X| B v -> Z v|0.24 |7.73 |0.09 |0.02 |
| v_ssp0clk/z_int_clk_cg/donttouch_or2|||||||
| dig_top_inst/apb1_inst/sys_config_inst/clkmux_inst | MUX2HD4X| B v -> Z v|0.29 |8.02 |0.13 |0.03 |
| _ssp0clk/donttouch_clkmux2|||||||
| dig_top_inst/ssp0_clk_Exclude_0| BUFCLKHD4X| A v -> Z v|0.32 |8.34 |0.25 |0.11 |
| dig_top_inst/sd_clk_gen/U58| AOI22HDLX| B v -> Z ^|0.25 |8.59 |0.28 |0.00 |
| dig_top_inst/sd_clk_gen/U6| OAI21HDLX| C ^ -> Z v|0.09 |8.68 |0.15 |0.00 |
| dig_top_inst/sd_clk_gen/U12| AOI21HDLX| C v -> Z ^|0.17 |8.85 |0.34 |0.01 |
| dig_top_inst/sd_clk_gen/U57| AOI32HDLX| D ^ -> Z v|0.15 |9.00 |0.21 |0.01 |
| dig_top_inst/sd_clk_gen/U69| AOI22HDLX| C v -> Z ^|0.19 |9.19 |0.31 |0.01 |
| dig_top_inst/sd_clk_gen/U68| AOI22HDLX| C ^ -> Z v|0.25 |9.44 |0.33 |0.02 |
| dig_top_inst/sd_clk_gen/sd_sample_clk_reg| LATNHD1X| D v -> Q v|0.35 |9.79 |0.14 |0.02 |
| dig_top_inst/a3ppo113_sd_clk_sample| BUFHD16X| A v -> Z v|0.23 |10.01 |0.14 |0.36 |
| dig_top_inst/sd_ctrl_top/U_DWC_mobile_storage_ciu/ | CLKGTNPHD4X | CKN v|0.12 |10.13 |0.25 |0.36 |
| U_DWC_mobile_storage_muxdemux/clk_gate_cdata_in_sa |||||||
| mple_2_reg/latch|||||||
+------------------------------------------------------------------------------------------------------------------+

为什么我的setup里的PHASESHIFT是100?

endpoint是下降沿触发的，startpoint是上升沿