关于在0.13um工艺下线阻的影响问题

最近在0.13工艺下做设计发现一些很有意思的现象，PT和ICC所报时序有较大差异的路径都是在IO单元后端存在较长连线的路径，换句话说连线的先祖对路径的时序影响不但很大，还在某种程度上导致了PT和ICC的时序报告的差异。想请教各位，是否遇到过这种情况，原因是什么?synopsys感觉不会公开二者算法的差异，所以寄希望于各位丰富的设计经验，多谢！

I have no experience on ICC. However, I think I could provide you some of my ideas based on my experiences with Encounter. Commonly, P&R tool can only have some information about wire delay from the wire delay model defined in .lib files. However, this information is not accurate. They are just some rough estimations of wire delays versus their fan-outs. So, by using these information, wire delay calculation would not be trusted in P&R. For STA in PT, the delay of wires are accurately extracted by some dedicated tools like QRC/Calibre. Parasitic effects are fully considered. So, PT can provide more accurate timing analysis results which may also be different from what P&R tool said. I think this is the main reason causing the phenomenon you see.
Sorry I cannot use Chinese currently, so I just use English

icc，pt相差很小，.13的时候电阻引起的delay也不大
贴个具体报告看看吧

库是我们自己建的，所以有些单元的性能可能不是很好。因为单位是保密机，报告贴不出来。但可以很肯定的是PT这边报出0.34的违例而ICC没有，并且在修改IO到第一级std_cell的连线距离后（调整IO端口位置），这个问题就没有了，比较两个cell之间连线较短的路径延时差别就不是很大，都是ps级别的。就是这个现象。同时两个软件报告出的相应单元的电容值和转移时间的差别也不是很大。

可以report delay calculation,也可以查timing table。看一下IO的output tran 有多敏感

十分感谢！